Analysis & Synthesis report for FTR_TOP
Thu Nov 26 13:16:51 2020
Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis IP Cores Summary
 10. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|sl_int_detect_state[0]
 11. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|sl_int_detect_state[1]
 12. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_state
 13. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_state
 14. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_state_ack
 15. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_state[0]
 16. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_state[1]
 17. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX|sl_int_state
 18. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX|sl_int_state
 19. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX|sl_int_state
 20. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX|sl_int_state
 21. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX|sl_int_state
 22. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX|sl_int_state
 23. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX|sl_int_state
 24. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX|sl_int_state
 25. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED|sl_int_state
 26. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED|sl_int_state
 27. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED|sl_int_state
 28. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED|sl_int_state
 29. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED|sl_int_state
 30. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED|sl_int_state
 31. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED|sl_int_state
 32. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED|sl_int_state
 33. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_mux
 34. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_timeout_state
 35. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_L1A_state
 36. State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_state
 37. State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_state
 38. State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET|sl_int_state
 39. State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_state
 40. State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET|sl_int_state
 41. State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_state
 42. State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET|sl_int_state
 43. State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_state
 44. State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|sl_int_state
 45. State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER|sl_int_state
 46. State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_timeout_state
 47. State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_process_state
 48. State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state
 49. State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_timeout_state
 50. State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state
 51. State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_state
 52. State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_state
 53. State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_start_state
 54. State Machine - |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|sl_int_state
 55. State Machine - |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE|sl_int_state
 56. State Machine - |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state
 57. Registers Protected by Synthesis
 58. Registers Removed During Synthesis
 59. Removed Registers Triggering Further Register Optimizations
 60. General Register Statistics
 61. Inverted Register Statistics
 62. Multiplexer Restructuring Statistics (Restructuring Performed)
 63. Source assignments for Top-level Entity: |FTR_TOP
 64. Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER
 65. Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i
 66. Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0
 67. Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1
 68. Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2
 69. Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3
 70. Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4
 71. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component
 72. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
 73. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component
 74. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated
 75. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_bg6:rdptr_g1p
 76. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_7ub:wrptr_g1p
 77. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|altsyncram_cia1:fifo_ram
 78. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:rs_brp
 79. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:rs_bwp
 80. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp
 81. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13
 82. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_brp
 83. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_bwp
 84. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp
 85. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16
 86. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated
 87. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_cu6:rdptr_g1p
 88. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_9cc:wrptr_g1p
 89. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|altsyncram_po91:fifo_ram
 90. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp
 91. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12
 92. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_brp
 93. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_bwp
 94. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp
 95. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16
 96. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|cntr_osd:cntr_b
 97. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated
 98. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_du6:rdptr_g1p
 99. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_8cc:wrptr_g1p
100. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|altsyncram_qo91:fifo_ram
101. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp
102. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12
103. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp
104. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15
105. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|cntr_osd:cntr_b
106. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component
107. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated
108. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_uv6:rdptr_g1p
109. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_qdc:wrptr_g1p
110. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram
111. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_6f9:rs_brp
112. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_6f9:rs_bwp
113. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp
114. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15
115. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_6f9:ws_brp
116. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_6f9:ws_bwp
117. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp
118. Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18
119. Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET
120. Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET
121. Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET
122. Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET
123. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component
124. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
125. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
126. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
127. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
128. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
129. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
130. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
131. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
132. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
133. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
134. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
135. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
136. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component
137. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
138. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
139. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
140. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
141. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
142. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
143. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
144. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
145. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
146. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
147. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
148. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
149. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component
150. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
151. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
152. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
153. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
154. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
155. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
156. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
157. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
158. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
159. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
160. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
161. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
162. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component
163. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
164. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
165. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
166. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
167. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
168. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
169. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
170. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
171. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
172. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
173. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
174. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
175. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component
176. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
177. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
178. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
179. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
180. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
181. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
182. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
183. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
184. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
185. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
186. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
187. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
188. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component
189. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
190. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
191. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
192. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
193. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
194. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
195. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
196. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
197. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
198. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
199. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
200. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
201. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component
202. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
203. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
204. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
205. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
206. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
207. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
208. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
209. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
210. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
211. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
212. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
213. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
214. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component
215. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
216. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
217. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
218. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
219. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
220. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
221. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
222. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
223. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
224. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
225. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
226. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
227. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component
228. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
229. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
230. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
231. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
232. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
233. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
234. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
235. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
236. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
237. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
238. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
239. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
240. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component
241. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
242. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
243. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
244. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
245. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
246. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
247. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
248. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
249. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
250. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
251. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
252. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
253. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component
254. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
255. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
256. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
257. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
258. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
259. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
260. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
261. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
262. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
263. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
264. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
265. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
266. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component
267. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
268. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
269. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
270. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
271. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
272. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
273. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
274. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
275. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
276. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
277. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
278. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
279. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component
280. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
281. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
282. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
283. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
284. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
285. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
286. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
287. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
288. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
289. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
290. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
291. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
292. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component
293. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
294. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
295. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
296. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
297. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
298. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
299. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
300. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
301. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
302. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
303. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
304. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
305. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component
306. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
307. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
308. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
309. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
310. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
311. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
312. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
313. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
314. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
315. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
316. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
317. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
318. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component
319. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated
320. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p
321. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p
322. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram
323. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp
324. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp
325. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp
326. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13
327. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp
328. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp
329. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp
330. Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16
331. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
332. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
333. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
334. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
335. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
336. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
337. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
338. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
339. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
340. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
341. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
342. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
343. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
344. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
345. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
346. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
347. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
348. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
349. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
350. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
351. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
352. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
353. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
354. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
355. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
356. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
357. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
358. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
359. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
360. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
361. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
362. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
363. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
364. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
365. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
366. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
367. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
368. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
369. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
370. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
371. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
372. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
373. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
374. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
375. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
376. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
377. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
378. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
379. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
380. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
381. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
382. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
383. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
384. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
385. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
386. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
387. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
388. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
389. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
390. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
391. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
392. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
393. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
394. Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
395. Parameter Settings for User Entity Instance: FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i
396. Parameter Settings for User Entity Instance: FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i
397. Parameter Settings for User Entity Instance: FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE
398. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB
399. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB
400. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component
401. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component
402. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC
403. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC
404. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER
405. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER
406. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART
407. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1
408. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART
409. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_bdgen:\g_dbgen:C_BDGEN
410. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER
411. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER
412. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component
413. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component
414. Parameter Settings for User Entity Instance: FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component
415. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS
416. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET
417. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET
418. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET
419. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET
420. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET
421. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET
422. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET
423. Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SETGET_ACK:C_GET_ACK
424. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER
425. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM
426. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM
427. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED
428. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED
429. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED
430. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED
431. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED
432. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED
433. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED
434. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED
435. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX
436. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX
437. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX
438. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX
439. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX
440. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX
441. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX
442. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX
443. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component
444. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component
445. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component
446. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component
447. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component
448. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component
449. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component
450. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component
451. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component
452. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component
453. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component
454. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component
455. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component
456. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component
457. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component
458. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component
459. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC
460. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM
461. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0
462. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1
463. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
464. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
465. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
466. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component
467. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
468. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
469. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
470. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component
471. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
472. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
473. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
474. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component
475. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
476. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
477. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
478. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component
479. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
480. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
481. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
482. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component
483. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
484. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
485. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
486. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component
487. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
488. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
489. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
490. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component
491. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
492. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
493. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
494. Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component
495. dcfifo Parameter Settings by Entity Instance
496. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1"
497. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1"
498. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1"
499. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1"
500. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1"
501. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1"
502. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1"
503. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1"
504. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0"
505. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0"
506. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0"
507. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0"
508. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0"
509. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0"
510. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0"
511. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0"
512. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX"
513. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX"
514. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX"
515. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX"
516. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX"
517. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX"
518. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX"
519. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX"
520. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED"
521. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED"
522. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED"
523. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED"
524. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED"
525. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED"
526. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED"
527. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED"
528. Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER"
529. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET"
530. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET"
531. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET"
532. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET"
533. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET"
534. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET"
535. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET"
536. Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS"
537. Port Connectivity Checks: "FTR_L2_FIFO:C_L2_FIFO"
538. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER"
539. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER"
540. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_bdgen:\g_dbgen:C_BDGEN"
541. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART"
542. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER"
543. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC"
544. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK"
545. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB"
546. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB"
547. Port Connectivity Checks: "FTR_CLK_WRAPPER:C_CLK_WRAPPER"
548. Post-Synthesis Netlist Statistics for Top Partition
549. Elapsed Time Per Partition
550. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2018  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details.



+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                      ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status     ; Successful - Thu Nov 26 13:16:50 2020           ;
; Quartus Prime Version           ; 18.0.0 Build 614 04/24/2018 SJ Standard Edition ;
; Revision Name                   ; FTR_TOP                                         ;
; Top-level Entity Name           ; FTR_TOP                                         ;
; Family                          ; Cyclone V                                       ;
; Logic utilization (in ALMs)     ; N/A                                             ;
; Total registers                 ; 5252                                            ;
; Total pins                      ; 203                                             ;
; Total virtual pins              ; 0                                               ;
; Total block memory bits         ; 3,020,864                                       ;
; Total DSP Blocks                ; 0                                               ;
; Total HSSI RX PCSs              ; 0                                               ;
; Total HSSI PMA RX Deserializers ; 0                                               ;
; Total HSSI TX PCSs              ; 0                                               ;
; Total HSSI PMA TX Serializers   ; 0                                               ;
; Total PLLs                      ; 2                                               ;
; Total DLLs                      ; 0                                               ;
+---------------------------------+-------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                             ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                          ; Setting            ; Default Value      ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                          ; 5CEBA7F23C8        ;                    ;
; Top-level entity name                                                           ; FTR_TOP            ; FTR_TOP            ;
; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
; VHDL Show LMF Mapping Messages                                                  ; Off                ;                    ;
; VHDL Version                                                                    ; VHDL_2008          ; VHDL_1993          ;
; Use smart compilation                                                           ; Off                ; Off                ;
; Enable parallel Assembler and Timing Analyzer during compilation                ; On                 ; On                 ;
; Enable compact report table                                                     ; Off                ; Off                ;
; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
; Preserve fewer node names                                                       ; On                 ; On                 ;
; Intel FPGA IP Evaluation Mode                                                   ; Enable             ; Enable             ;
; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
; State Machine Processing                                                        ; Auto               ; Auto               ;
; Safe State Machine                                                              ; Off                ; Off                ;
; Extract Verilog State Machines                                                  ; On                 ; On                 ;
; Extract VHDL State Machines                                                     ; On                 ; On                 ;
; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
; Parallel Synthesis                                                              ; On                 ; On                 ;
; DSP Block Balancing                                                             ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                              ; On                 ; On                 ;
; Power-Up Don't Care                                                             ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
; Remove Duplicate Registers                                                      ; On                 ; On                 ;
; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
; Optimization Technique                                                          ; Balanced           ; Balanced           ;
; Carry Chain Length                                                              ; 70                 ; 70                 ;
; Auto Carry Chains                                                               ; On                 ; On                 ;
; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
; Auto ROM Replacement                                                            ; On                 ; On                 ;
; Auto RAM Replacement                                                            ; On                 ; On                 ;
; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
; Strict RAM Replacement                                                          ; Off                ; Off                ;
; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                           ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
; Report Parameter Settings                                                       ; On                 ; On                 ;
; Report Source Assignments                                                       ; On                 ; On                 ;
; Report Connectivity Checks                                                      ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
; Power Optimization During Synthesis                                             ; Normal compilation ; Normal compilation ;
; HDL message level                                                               ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                            ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
; Block Design Naming                                                             ; Auto               ; Auto               ;
; SDC constraint protection                                                       ; Off                ; Off                ;
; Synthesis Effort                                                                ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
+---------------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   0.0%      ;
;     Processor 3            ;   0.0%      ;
;     Processor 4            ;   0.0%      ;
+----------------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                                                 ;
+--------------------------------------------------------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------------+----------+
; File Name with User-Entered Path                                               ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                              ; Library  ;
+--------------------------------------------------------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------------+----------+
; ../../lib/u_util/exp/u_size.vhd                                                ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/u_util/exp/u_size.vhd                                                ;          ;
; ../../lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd                            ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd                            ;          ;
; ../../lib/usb_usb/exp/USB_USB.vhd                                              ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/usb_usb/exp/USB_USB.vhd                                              ;          ;
; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                               ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                               ;          ;
; ../../lib/usb_usb/src/USB_USB_Reader.vhd                                       ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/usb_usb/src/USB_USB_Reader.vhd                                       ;          ;
; ../../lib/ser_serialCommunication/exp/ser_serialCommunication.vhd              ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/exp/ser_serialCommunication.vhd              ;          ;
; ../../lib/ser_serialCommunication/exp/ser_crc_pck.vhd                          ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/exp/ser_crc_pck.vhd                          ;          ;
; ../../lib/ser_serialCommunication/src/ser_crc_pck_polynomial.vhd               ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc_pck_polynomial.vhd               ;          ;
; ../../lib/ser_serialCommunication/src/ser_crc.vhd                              ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc.vhd                              ;          ;
; ../../lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd ;          ;
; ../../lib/ser_serialCommunication/src/ser_uart_ser.vhd                         ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_ser.vhd                         ;          ;
; ../../lib/ser_serialCommunication/src/ser_uart_deser.vhd                       ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_deser.vhd                       ;          ;
; ../../lib/ser_serialCommunication/src/ser_data_5_bits_filter.vhd               ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_data_5_bits_filter.vhd               ;          ;
; ../../lib/ser_serialCommunication/src/ser_uart_bdgen.vhd                       ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_bdgen.vhd                       ;          ;
; ../../lib/ser_serialCommunication/src/ser_uart.vhd                             ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart.vhd                             ;          ;
; ../../lib/ser_serialCommunication/src/ser_uart_wrapper.vhd                     ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper.vhd                     ;          ;
; ../../lib/ser_serialCommunication/src/ser_uart_wrapper32.vhd                   ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper32.vhd                   ;          ;
; ../../lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd        ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd        ;          ;
; ../../lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd        ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd        ;          ;
; ../../lib/UFP_UsbFrontEndProtocol/exp/UFP_UsbFrontEndProtocol.vhd              ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_UsbFrontEndProtocol.vhd              ;          ;
; ../../lib/UFP_UsbFrontEndProtocol/exp/UFP_Protocol.vhd                         ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_Protocol.vhd                         ;          ;
; ../../lib/UFP_UsbFrontEndProtocol/exp/UFP_fw_version.vhd                       ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_fw_version.vhd                       ;          ;
; ../../lib/UFP_UsbFrontEndProtocol/src/UFP_Decoder.vhd                          ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Decoder.vhd                          ;          ;
; ../../lib/UFP_UsbFrontEndProtocol/src/UFP_Encoder_uart.vhd                     ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Encoder_uart.vhd                     ;          ;
; ../../lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd                 ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd                 ;          ;
; ../../lib/UFP_UsbFrontEndProtocol/src/UFP_USER_GET_CONFIG.vhd                  ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_GET_CONFIG.vhd                  ;          ;
; ../../lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SET_CONFIG.vhd                  ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SET_CONFIG.vhd                  ;          ;
; ../../lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SETGET_ACK.vhd                  ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SETGET_ACK.vhd                  ;          ;
; src/PLL_MAIN.vhd                                                               ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN.vhd                         ; PLL_MAIN ;
; src/PLL_MAIN/PLL_MAIN_0002.v                                                   ; yes             ; User Verilog HDL File        ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN/PLL_MAIN_0002.v             ; PLL_MAIN ;
; src/PLL_4K.vhd                                                                 ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K.vhd                           ; PLL_4K   ;
; src/PLL_4K/PLL_4K_0002.v                                                       ; yes             ; User Verilog HDL File        ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K/PLL_4K_0002.v                 ; PLL_4K   ;
; src/FTR_FINE_PHASE_SM.vhd                                                      ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FINE_PHASE_SM.vhd                ;          ;
; src/FTR_PatchPanelControllerSM.vhd                                             ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PatchPanelControllerSM.vhd       ;          ;
; src/FTR_PlaneControllerSM.vhd                                                  ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneControllerSM.vhd            ;          ;
; src/FTR_PlaneController.vhd                                                    ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneController.vhd              ;          ;
; src/FTR_RXDataModuleManager.vhd                                                ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataModuleManager.vhd          ;          ;
; src/FTR_RXDataPlaneManager.vhd                                                 ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataPlaneManager.vhd           ;          ;
; src/FTR_L2_SM.vhd                                                              ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_SM.vhd                        ;          ;
; src/FTR_FaserWrapper.vhd                                                       ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FaserWrapper.vhd                 ;          ;
; src/FTR_CLK_WRAPPER.vhd                                                        ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_CLK_WRAPPER.vhd                  ;          ;
; src/FTR_REG_WRAPPER.vhd                                                        ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd                  ;          ;
; src/FTR_L2_FIFO.vhd                                                            ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_FIFO.vhd                      ;          ;
; src/FTR_L1_FIFO.vhd                                                            ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L1_FIFO.vhd                      ;          ;
; src/FTR_GLOBAL_CONST.vhd                                                       ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_GLOBAL_CONST.vhd                 ;          ;
; src/FTR_TOP.vhd                                                                ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd                          ;          ;
; altera_pll.v                                                                   ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v                            ;          ;
; altera_pll_dps_lcell_comb.v                                                    ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v             ;          ;
; altera_cyclonev_pll.v                                                          ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v                   ;          ;
; altddio_out.tdf                                                                ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altddio_out.tdf                         ;          ;
; aglobal180.inc                                                                 ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/aglobal180.inc                          ;          ;
; stratix_ddio.inc                                                               ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/stratix_ddio.inc                        ;          ;
; cyclone_ddio.inc                                                               ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/cyclone_ddio.inc                        ;          ;
; lpm_mux.inc                                                                    ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_mux.inc                             ;          ;
; stratix_lcell.inc                                                              ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/stratix_lcell.inc                       ;          ;
; db/ddio_out_b2j.tdf                                                            ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/ddio_out_b2j.tdf                      ;          ;
; dcfifo.tdf                                                                     ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf                              ;          ;
; lpm_counter.inc                                                                ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_counter.inc                         ;          ;
; lpm_add_sub.inc                                                                ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_add_sub.inc                         ;          ;
; altdpram.inc                                                                   ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altdpram.inc                            ;          ;
; a_graycounter.inc                                                              ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_graycounter.inc                       ;          ;
; a_fefifo.inc                                                                   ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fefifo.inc                            ;          ;
; a_gray2bin.inc                                                                 ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_gray2bin.inc                          ;          ;
; dffpipe.inc                                                                    ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/dffpipe.inc                             ;          ;
; alt_sync_fifo.inc                                                              ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/alt_sync_fifo.inc                       ;          ;
; lpm_compare.inc                                                                ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_compare.inc                         ;          ;
; altsyncram_fifo.inc                                                            ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram_fifo.inc                     ;          ;
; db/dcfifo_85n1.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_85n1.tdf                       ;          ;
; db/a_gray2bin_e9b.tdf                                                          ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_gray2bin_e9b.tdf                    ;          ;
; db/a_graycounter_bg6.tdf                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_bg6.tdf                 ;          ;
; db/a_graycounter_7ub.tdf                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_7ub.tdf                 ;          ;
; db/altsyncram_cia1.tdf                                                         ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/altsyncram_cia1.tdf                   ;          ;
; db/dffpipe_vu8.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_vu8.tdf                       ;          ;
; db/alt_synch_pipe_f9l.tdf                                                      ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_f9l.tdf                ;          ;
; db/dffpipe_0v8.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_0v8.tdf                       ;          ;
; db/alt_synch_pipe_g9l.tdf                                                      ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_g9l.tdf                ;          ;
; db/dffpipe_1v8.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_1v8.tdf                       ;          ;
; db/cmpr_vu5.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/cmpr_vu5.tdf                          ;          ;
; dcfifo_mixed_widths.tdf                                                        ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo_mixed_widths.tdf                 ;          ;
; db/dcfifo_8tq1.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_8tq1.tdf                       ;          ;
; db/a_graycounter_cu6.tdf                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_cu6.tdf                 ;          ;
; db/a_graycounter_9cc.tdf                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_9cc.tdf                 ;          ;
; db/altsyncram_po91.tdf                                                         ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/altsyncram_po91.tdf                   ;          ;
; db/alt_synch_pipe_unl.tdf                                                      ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_unl.tdf                ;          ;
; db/dffpipe_fd9.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_fd9.tdf                       ;          ;
; db/dffpipe_ed9.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_ed9.tdf                       ;          ;
; db/alt_synch_pipe_vnl.tdf                                                      ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_vnl.tdf                ;          ;
; db/dffpipe_gd9.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_gd9.tdf                       ;          ;
; db/cntr_osd.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/cntr_osd.tdf                          ;          ;
; db/dcfifo_a5q1.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_a5q1.tdf                       ;          ;
; db/a_graycounter_du6.tdf                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_du6.tdf                 ;          ;
; db/a_graycounter_8cc.tdf                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_8cc.tdf                 ;          ;
; db/altsyncram_qo91.tdf                                                         ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/altsyncram_qo91.tdf                   ;          ;
; db/alt_synch_pipe_0ol.tdf                                                      ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_0ol.tdf                ;          ;
; db/dffpipe_hd9.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_hd9.tdf                       ;          ;
; db/alt_synch_pipe_1ol.tdf                                                      ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_1ol.tdf                ;          ;
; db/dffpipe_id9.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_id9.tdf                       ;          ;
; db/dcfifo_kvr1.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_kvr1.tdf                       ;          ;
; db/a_gray2bin_vab.tdf                                                          ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_gray2bin_vab.tdf                    ;          ;
; db/a_graycounter_uv6.tdf                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_uv6.tdf                 ;          ;
; db/a_graycounter_qdc.tdf                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_qdc.tdf                 ;          ;
; db/altsyncram_29d1.tdf                                                         ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/altsyncram_29d1.tdf                   ;          ;
; db/decode_417.tdf                                                              ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/decode_417.tdf                        ;          ;
; db/mux_2t7.tdf                                                                 ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/mux_2t7.tdf                           ;          ;
; db/dffpipe_6f9.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_6f9.tdf                       ;          ;
; db/alt_synch_pipe_ipl.tdf                                                      ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_ipl.tdf                ;          ;
; db/dffpipe_7f9.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_7f9.tdf                       ;          ;
; db/alt_synch_pipe_jpl.tdf                                                      ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_jpl.tdf                ;          ;
; db/dffpipe_8f9.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_8f9.tdf                       ;          ;
; db/cmpr_g06.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/cmpr_g06.tdf                          ;          ;
; db/dcfifo_jtr1.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_jtr1.tdf                       ;          ;
; db/a_gray2bin_qab.tdf                                                          ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_gray2bin_qab.tdf                    ;          ;
; db/a_graycounter_pv6.tdf                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_pv6.tdf                 ;          ;
; db/a_graycounter_ldc.tdf                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_ldc.tdf                 ;          ;
; db/altsyncram_t8d1.tdf                                                         ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/altsyncram_t8d1.tdf                   ;          ;
; db/dffpipe_qe9.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_qe9.tdf                       ;          ;
; db/alt_synch_pipe_apl.tdf                                                      ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_apl.tdf                ;          ;
; db/dffpipe_re9.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_re9.tdf                       ;          ;
; db/alt_synch_pipe_bpl.tdf                                                      ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_bpl.tdf                ;          ;
; db/dffpipe_ve9.tdf                                                             ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_ve9.tdf                       ;          ;
; db/cmpr_b06.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/cmpr_b06.tdf                          ;          ;
+--------------------------------------------------------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------------+----------+


+--------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                        ;
+---------------------------------------------+----------------------+
; Resource                                    ; Usage                ;
+---------------------------------------------+----------------------+
; Estimate of Logic utilization (ALMs needed) ; 4087                 ;
;                                             ;                      ;
; Combinational ALUT usage for logic          ; 5380                 ;
;     -- 7 input functions                    ; 23                   ;
;     -- 6 input functions                    ; 2111                 ;
;     -- 5 input functions                    ; 682                  ;
;     -- 4 input functions                    ; 704                  ;
;     -- <=3 input functions                  ; 1860                 ;
;                                             ;                      ;
; Dedicated logic registers                   ; 5186                 ;
;                                             ;                      ;
; I/O pins                                    ; 203                  ;
; I/O registers                               ; 66                   ;
; Total MLAB memory bits                      ; 0                    ;
; Total block memory bits                     ; 3020864              ;
;                                             ;                      ;
; Total DSP Blocks                            ; 0                    ;
;                                             ;                      ;
; Total PLLs                                  ; 3                    ;
;     -- PLLs                                 ; 2                    ;
;     -- Fractional PLLs                      ; 1                    ;
;                                             ;                      ;
; Maximum fan-out node                        ; sl_int_dpar_latch[4] ;
; Maximum fan-out                             ; 3055                 ;
; Total fan-out                               ; 62844                ;
; Average fan-out                             ; 5.33                 ;
+---------------------------------------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+--------------+
; Compilation Hierarchy Node                                         ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                       ; Entity Name                  ; Library Name ;
+--------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+--------------+
; |FTR_TOP                                                           ; 5380 (18)           ; 5186 (19)                 ; 3020864           ; 0          ; 203  ; 0            ; |FTR_TOP                                                                                                                                                                                                                                                  ; FTR_TOP                      ; work         ;
;    |FTR_CLK_WRAPPER:C_CLK_WRAPPER|                                 ; 119 (52)            ; 65 (39)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER                                                                                                                                                                                                                    ; FTR_CLK_WRAPPER              ; work         ;
;       |FTR_FINE_PHASE_SM:C_PHASE_TUNE|                             ; 32 (32)             ; 20 (20)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE                                                                                                                                                                                     ; FTR_FINE_PHASE_SM            ; work         ;
;       |PLL_4K:C_PLL4|                                              ; 35 (0)              ; 6 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4                                                                                                                                                                                                      ; PLL_4K                       ; pll_4k       ;
;          |PLL_4K_0002:pll_4k_inst|                                 ; 35 (0)              ; 6 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst                                                                                                                                                                              ; PLL_4K_0002                  ; PLL_4K       ;
;             |altera_pll:altera_pll_i|                              ; 35 (23)             ; 6 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i                                                                                                                                                      ; altera_pll                   ; work         ;
;                |altera_cyclonev_pll:cyclonev_pll|                  ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll                                                                                                                     ; altera_cyclonev_pll          ; work         ;
;                   |altera_cyclonev_pll_base:fpll_0|                ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0                                                                                     ; altera_cyclonev_pll_base     ; work         ;
;                |altera_pll_dps_lcell_comb:lcell_cntsel_int_0|      ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0                                                                                                         ; altera_pll_dps_lcell_comb    ; work         ;
;                |altera_pll_dps_lcell_comb:lcell_cntsel_int_1|      ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1                                                                                                         ; altera_pll_dps_lcell_comb    ; work         ;
;                |altera_pll_dps_lcell_comb:lcell_cntsel_int_2|      ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2                                                                                                         ; altera_pll_dps_lcell_comb    ; work         ;
;                |altera_pll_dps_lcell_comb:lcell_cntsel_int_3|      ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3                                                                                                         ; altera_pll_dps_lcell_comb    ; work         ;
;                |altera_pll_dps_lcell_comb:lcell_cntsel_int_4|      ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4                                                                                                         ; altera_pll_dps_lcell_comb    ; work         ;
;                |dps_extra_kick:dps_extra_inst|                     ; 7 (7)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst                                                                                                                        ; dps_extra_kick               ; work         ;
;       |PLL_MAIN:C_PLL|                                             ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL                                                                                                                                                                                                     ; PLL_MAIN                     ; pll_main     ;
;          |PLL_MAIN_0002:pll_main_inst|                             ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst                                                                                                                                                                         ; PLL_MAIN_0002                ; PLL_MAIN     ;
;             |altera_pll:altera_pll_i|                              ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i                                                                                                                                                 ; altera_pll                   ; work         ;
;    |FTR_FaserWrapper:C_WRAPPER|                                    ; 4250 (12)           ; 3865 (24)                 ; 851968            ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER                                                                                                                                                                                                                       ; FTR_FaserWrapper             ; work         ;
;       |FTR_L2_SM:C_L2_SM|                                          ; 492 (492)           ; 227 (227)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM                                                                                                                                                                                                     ; FTR_L2_SM                    ; work         ;
;       |FTR_PlaneController:C_PC|                                   ; 626 (0)             ; 638 (4)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC                                                                                                                                                                                              ; FTR_PlaneController          ; work         ;
;          |FTR_PatchPanelControllerSM:C_PP_Controller0|             ; 258 (258)           ; 263 (263)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0                                                                                                                                                  ; FTR_PatchPanelControllerSM   ; work         ;
;          |FTR_PatchPanelControllerSM:C_PP_Controller1|             ; 262 (262)           ; 263 (263)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1                                                                                                                                                  ; FTR_PatchPanelControllerSM   ; work         ;
;          |FTR_PlaneControllerSM:C_PC_SM|                           ; 106 (106)           ; 108 (108)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM                                                                                                                                                                ; FTR_PlaneControllerSM        ; work         ;
;       |FTR_RXDataPlaneManager:C_RXDPM|                             ; 3120 (4)            ; 2976 (16)                 ; 851968            ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM                                                                                                                                                                                        ; FTR_RXDataPlaneManager       ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|                   ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED                                                                                                                                                  ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                          ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 88 (16)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                               ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                   ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 22 (22)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                   ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                    ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                              ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                    ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                              ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                      ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                      ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                       ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                            ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                            ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|                   ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED                                                                                                                                                  ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                          ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 88 (16)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                               ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                   ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 22 (22)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                   ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                    ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                              ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                    ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                              ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                      ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                      ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                       ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                            ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                            ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|                   ; 89 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED                                                                                                                                                  ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 89 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                          ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 89 (17)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                               ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                   ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 22 (22)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                   ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                    ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                              ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                    ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                              ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                      ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                      ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                       ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                            ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                            ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|                   ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED                                                                                                                                                  ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                          ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 88 (17)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                               ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                   ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 21 (21)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                   ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                    ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                              ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                    ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                              ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                      ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                      ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                       ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                            ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                            ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|                   ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED                                                                                                                                                  ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                          ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 88 (16)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                               ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                   ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 22 (22)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                   ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                    ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                              ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                    ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                              ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                      ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                      ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                       ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                            ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                            ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|                   ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED                                                                                                                                                  ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                          ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 88 (16)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                               ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                   ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 22 (22)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                   ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                    ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                              ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                    ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                              ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                      ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                      ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                       ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                            ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                            ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|                   ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED                                                                                                                                                  ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                          ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 88 (16)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                               ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                   ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 22 (22)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                   ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                    ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                              ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                    ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                              ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                      ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                      ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                       ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                            ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                            ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|                   ; 87 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED                                                                                                                                                  ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 87 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component                                                                                                                          ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 87 (16)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                               ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                               ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                   ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 21 (21)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                   ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                    ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                              ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                    ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                              ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                      ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                      ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                       ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                            ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                            ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|                 ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX                                                                                                                                                ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                        ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 88 (16)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                             ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                 ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 22 (22)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                 ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                  ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                            ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                  ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                            ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                    ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                    ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                     ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                          ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                          ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|                 ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX                                                                                                                                                ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                        ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 88 (16)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                             ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                 ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 22 (22)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                 ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                  ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                            ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                  ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                            ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                    ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                    ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                     ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                          ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                          ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|                 ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX                                                                                                                                                ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                        ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 88 (16)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                             ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                 ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 22 (22)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                 ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                  ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                            ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                  ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                            ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                    ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                    ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                     ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                          ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                          ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|                 ; 87 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX                                                                                                                                                ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 87 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                        ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 87 (16)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                             ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                 ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 21 (21)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                 ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                  ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                            ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                  ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                            ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                    ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                    ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                     ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                          ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                          ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|                 ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX                                                                                                                                                ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                        ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 88 (16)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                             ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                 ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 22 (22)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                 ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                  ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                            ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                  ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                            ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                    ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                    ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                     ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                          ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                          ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|                 ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX                                                                                                                                                ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                        ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 88 (16)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                             ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                 ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 22 (22)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                 ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                  ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                            ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                  ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                            ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                    ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                    ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                     ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                          ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                          ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|                 ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX                                                                                                                                                ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 88 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                        ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 88 (16)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                             ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                 ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 22 (22)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                 ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                  ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                            ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                  ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                            ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                    ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                    ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                     ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                          ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                          ; dffpipe_qe9                  ; work         ;
;          |FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|                 ; 87 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX                                                                                                                                                ; FTR_L1_FIFO                  ; work         ;
;             |dcfifo:dcfifo_component|                              ; 87 (0)              ; 136 (0)                   ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component                                                                                                                        ; dcfifo                       ; work         ;
;                |dcfifo_jtr1:auto_generated|                        ; 87 (16)             ; 136 (36)                  ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated                                                                                             ; dcfifo_jtr1                  ; work         ;
;                   |a_gray2bin_qab:wrptr_g_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:wrptr_g_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_gray2bin_qab:ws_dgrp_gray2bin|                ; 11 (11)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:ws_dgrp_gray2bin                                                             ; a_gray2bin_qab               ; work         ;
;                   |a_graycounter_ldc:wrptr_g1p|                    ; 18 (18)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p                                                                 ; a_graycounter_ldc            ; work         ;
;                   |a_graycounter_pv6:rdptr_g1p|                    ; 21 (21)             ; 15 (15)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p                                                                 ; a_graycounter_pv6            ; work         ;
;                   |alt_synch_pipe_apl:rs_dgwp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp                                                                  ; alt_synch_pipe_apl           ; work         ;
;                      |dffpipe_re9:dffpipe13|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13                                            ; dffpipe_re9                  ; work         ;
;                   |alt_synch_pipe_bpl:ws_dgrp|                     ; 0 (0)               ; 24 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp                                                                  ; alt_synch_pipe_bpl           ; work         ;
;                      |dffpipe_ve9:dffpipe16|                       ; 0 (0)               ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16                                            ; dffpipe_ve9                  ; work         ;
;                   |altsyncram_t8d1:fifo_ram|                       ; 0 (0)               ; 0 (0)                     ; 53248             ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram                                                                    ; altsyncram_t8d1              ; work         ;
;                   |cmpr_b06:rdempty_eq_comp|                       ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp                                                                    ; cmpr_b06                     ; work         ;
;                   |cmpr_b06:wrfull_eq_comp|                        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:wrfull_eq_comp                                                                     ; cmpr_b06                     ; work         ;
;                   |dffpipe_qe9:ws_brp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp                                                                          ; dffpipe_qe9                  ; work         ;
;                   |dffpipe_qe9:ws_bwp|                             ; 0 (0)               ; 11 (11)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp                                                                          ; dffpipe_qe9                  ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED|      ; 107 (107)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED                                                                                                                                     ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED|      ; 107 (107)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED                                                                                                                                     ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED|      ; 107 (107)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED                                                                                                                                     ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED|      ; 107 (107)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED                                                                                                                                     ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED|      ; 107 (107)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED                                                                                                                                     ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED|      ; 107 (107)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED                                                                                                                                     ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED|      ; 107 (107)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED                                                                                                                                     ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED|      ; 107 (107)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED                                                                                                                                     ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX|    ; 107 (107)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX                                                                                                                                   ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX|    ; 107 (107)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX                                                                                                                                   ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX|    ; 107 (107)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX                                                                                                                                   ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX|    ; 106 (106)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX                                                                                                                                   ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX|    ; 107 (107)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX                                                                                                                                   ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX|    ; 107 (107)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX                                                                                                                                   ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX|    ; 107 (107)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX                                                                                                                                   ; FTR_RXDataModuleManager      ; work         ;
;          |FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX|    ; 106 (106)           ; 49 (49)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX                                                                                                                                   ; FTR_RXDataModuleManager      ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;       |USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1                                                                                                                                                                              ; USB_UC_PCLK                  ; work         ;
;          |altddio_out:ALTDDIO_OUT_component|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component                                                                                                                                            ; altddio_out                  ; work         ;
;             |ddio_out_b2j:auto_generated|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                                ; ddio_out_b2j                 ; work         ;
;    |FTR_L2_FIFO:C_L2_FIFO|                                         ; 231 (0)             ; 202 (0)                   ; 2162688           ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO                                                                                                                                                                                                                            ; FTR_L2_FIFO                  ; work         ;
;       |dcfifo:dcfifo_component|                                    ; 231 (0)             ; 202 (0)                   ; 2162688           ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component                                                                                                                                                                                                    ; dcfifo                       ; work         ;
;          |dcfifo_kvr1:auto_generated|                              ; 231 (20)            ; 202 (51)                  ; 2162688           ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated                                                                                                                                                                         ; dcfifo_kvr1                  ; work         ;
;             |a_gray2bin_vab:wrptr_g_gray2bin|                      ; 16 (16)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_gray2bin_vab:wrptr_g_gray2bin                                                                                                                                         ; a_gray2bin_vab               ; work         ;
;             |a_gray2bin_vab:ws_dgrp_gray2bin|                      ; 16 (16)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_gray2bin_vab:ws_dgrp_gray2bin                                                                                                                                         ; a_gray2bin_vab               ; work         ;
;             |a_graycounter_qdc:wrptr_g1p|                          ; 25 (25)             ; 21 (21)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_qdc:wrptr_g1p                                                                                                                                             ; a_graycounter_qdc            ; work         ;
;             |a_graycounter_uv6:rdptr_g1p|                          ; 30 (30)             ; 21 (21)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_uv6:rdptr_g1p                                                                                                                                             ; a_graycounter_uv6            ; work         ;
;             |alt_synch_pipe_ipl:rs_dgwp|                           ; 0 (0)               ; 34 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp                                                                                                                                              ; alt_synch_pipe_ipl           ; work         ;
;                |dffpipe_7f9:dffpipe15|                             ; 0 (0)               ; 34 (34)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15                                                                                                                        ; dffpipe_7f9                  ; work         ;
;             |alt_synch_pipe_jpl:ws_dgrp|                           ; 0 (0)               ; 34 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp                                                                                                                                              ; alt_synch_pipe_jpl           ; work         ;
;                |dffpipe_8f9:dffpipe18|                             ; 0 (0)               ; 34 (34)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18                                                                                                                        ; dffpipe_8f9                  ; work         ;
;             |altsyncram_29d1:fifo_ram|                             ; 110 (3)             ; 9 (9)                     ; 2162688           ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram                                                                                                                                                ; altsyncram_29d1              ; work         ;
;                |decode_417:decode12|                               ; 8 (8)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|decode_417:decode12                                                                                                                            ; decode_417                   ; work         ;
;                |mux_2t7:mux13|                                     ; 99 (99)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|mux_2t7:mux13                                                                                                                                  ; mux_2t7                      ; work         ;
;             |cmpr_g06:rdempty_eq_comp|                             ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|cmpr_g06:rdempty_eq_comp                                                                                                                                                ; cmpr_g06                     ; work         ;
;             |cmpr_g06:wrfull_eq_comp|                              ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|cmpr_g06:wrfull_eq_comp                                                                                                                                                 ; cmpr_g06                     ; work         ;
;             |dffpipe_6f9:ws_brp|                                   ; 0 (0)               ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_6f9:ws_brp                                                                                                                                                      ; dffpipe_6f9                  ; work         ;
;             |dffpipe_6f9:ws_bwp|                                   ; 0 (0)               ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_6f9:ws_bwp                                                                                                                                                      ; dffpipe_6f9                  ; work         ;
;    |FTR_REG_WRAPPER:C_REGS|                                        ; 119 (4)             ; 453 (0)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS                                                                                                                                                                                                                           ; FTR_REG_WRAPPER              ; work         ;
;       |UFP_USER_GET_CONFIG:C_CONFIG_USER_GET|                      ; 47 (47)             ; 24 (24)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET                                                                                                                                                                                     ; UFP_USER_GET_CONFIG          ; work         ;
;       |UFP_USER_GET_CONFIG:C_PHASE_USER_GET|                       ; 3 (3)               ; 20 (20)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET                                                                                                                                                                                      ; UFP_USER_GET_CONFIG          ; work         ;
;       |UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET|                    ; 20 (20)             ; 22 (22)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET                                                                                                                                                                                   ; UFP_USER_GET_CONFIG          ; work         ;
;       |UFP_USER_SETGET_ACK:C_GET_ACK|                              ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SETGET_ACK:C_GET_ACK                                                                                                                                                                                             ; UFP_USER_SETGET_ACK          ; work         ;
;       |UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|                      ; 14 (14)             ; 124 (124)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET                                                                                                                                                                                     ; UFP_USER_SET_CONFIG          ; work         ;
;       |UFP_USER_SET_CONFIG:C_PHASE_USER_SET|                       ; 4 (4)               ; 33 (33)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET                                                                                                                                                                                      ; UFP_USER_SET_CONFIG          ; work         ;
;       |UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|                    ; 19 (19)             ; 184 (184)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET                                                                                                                                                                                   ; UFP_USER_SET_CONFIG          ; work         ;
;       |UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|                    ; 7 (7)               ; 46 (46)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET                                                                                                                                                                                   ; UFP_USER_SET_CONFIG          ; work         ;
;    |UFP_WRAPPER_USB_UART:C_WRAPPER_USB|                            ; 643 (3)             ; 582 (1)                   ; 6208              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB                                                                                                                                                                                                               ; UFP_WRAPPER_USB_UART         ; work         ;
;       |UFP_DECODER:C_DECODER|                                      ; 216 (216)           ; 95 (95)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER                                                                                                                                                                                         ; UFP_DECODER                  ; work         ;
;       |UFP_ENCODER_UART:C_ENCODER|                                 ; 143 (143)           ; 103 (103)                 ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER                                                                                                                                                                                    ; UFP_ENCODER_UART             ; work         ;
;       |USB_L2_TX_FIFO:C_FIFO_READOUT_TX|                           ; 53 (0)              ; 81 (0)                    ; 2112              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX                                                                                                                                                                              ; USB_L2_TX_FIFO               ; work         ;
;          |dcfifo:dcfifo_component|                                 ; 53 (0)              ; 81 (0)                    ; 2112              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component                                                                                                                                                      ; dcfifo                       ; work         ;
;             |dcfifo_85n1:auto_generated|                           ; 53 (12)             ; 81 (21)                   ; 2112              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated                                                                                                                           ; dcfifo_85n1                  ; work         ;
;                |a_gray2bin_e9b:wrptr_g_gray2bin|                   ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_gray2bin_e9b:wrptr_g_gray2bin                                                                                           ; a_gray2bin_e9b               ; work         ;
;                |a_gray2bin_e9b:ws_dgrp_gray2bin|                   ; 6 (6)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_gray2bin_e9b:ws_dgrp_gray2bin                                                                                           ; a_gray2bin_e9b               ; work         ;
;                |a_graycounter_7ub:wrptr_g1p|                       ; 11 (11)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_7ub:wrptr_g1p                                                                                               ; a_graycounter_7ub            ; work         ;
;                |a_graycounter_bg6:rdptr_g1p|                       ; 12 (12)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_bg6:rdptr_g1p                                                                                               ; a_graycounter_bg6            ; work         ;
;                |alt_synch_pipe_f9l:rs_dgwp|                        ; 0 (0)               ; 14 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp                                                                                                ; alt_synch_pipe_f9l           ; work         ;
;                   |dffpipe_0v8:dffpipe13|                          ; 0 (0)               ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13                                                                          ; dffpipe_0v8                  ; work         ;
;                |alt_synch_pipe_g9l:ws_dgrp|                        ; 0 (0)               ; 14 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp                                                                                                ; alt_synch_pipe_g9l           ; work         ;
;                   |dffpipe_1v8:dffpipe16|                          ; 0 (0)               ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16                                                                          ; dffpipe_1v8                  ; work         ;
;                |altsyncram_cia1:fifo_ram|                          ; 0 (0)               ; 0 (0)                     ; 2112              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|altsyncram_cia1:fifo_ram                                                                                                  ; altsyncram_cia1              ; work         ;
;                |cmpr_vu5:rdempty_eq_comp|                          ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|cmpr_vu5:rdempty_eq_comp                                                                                                  ; cmpr_vu5                     ; work         ;
;                |cmpr_vu5:wrfull_eq_comp|                           ; 3 (3)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|cmpr_vu5:wrfull_eq_comp                                                                                                   ; cmpr_vu5                     ; work         ;
;                |dffpipe_vu8:ws_brp|                                ; 0 (0)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_brp                                                                                                        ; dffpipe_vu8                  ; work         ;
;                |dffpipe_vu8:ws_bwp|                                ; 0 (0)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_bwp                                                                                                        ; dffpipe_vu8                  ; work         ;
;       |USB_USB_Reader:C_USB|                                       ; 38 (38)             ; 63 (63)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB                                                                                                                                                                                          ; USB_USB_Reader               ; work         ;
;          |USB_UC_PCLK:C_UC_PCLK|                                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK                                                                                                                                                                    ; USB_UC_PCLK                  ; work         ;
;             |altddio_out:ALTDDIO_OUT_component|                    ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component                                                                                                                                  ; altddio_out                  ; work         ;
;                |ddio_out_b2j:auto_generated|                       ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                      ; ddio_out_b2j                 ; work         ;
;       |ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|                         ; 35 (4)              ; 21 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC                                                                                                                                                                            ; ser_crc_pol16_DIN16_D4_1a2eb ; work         ;
;          |ser_crc:C_CRC|                                           ; 31 (31)             ; 21 (21)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC                                                                                                                                                              ; ser_crc                      ; work         ;
;       |ser_uart_wrapper:C_UART|                                    ; 155 (0)             ; 218 (0)                   ; 4096              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART                                                                                                                                                                                       ; ser_uart_wrapper             ; work         ;
;          |ser_uart_wrapper32:\g32:u1|                              ; 155 (0)             ; 218 (0)                   ; 4096              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1                                                                                                                                                            ; ser_uart_wrapper32           ; work         ;
;             |SER_UART_FIFO_RX32:C_FIFO_RX|                         ; 41 (0)              ; 73 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX                                                                                                                               ; SER_UART_FIFO_RX32           ; work         ;
;                |dcfifo_mixed_widths:dcfifo_mixed_widths_component| ; 41 (0)              ; 73 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component                                                                             ; dcfifo_mixed_widths          ; work         ;
;                   |dcfifo_a5q1:auto_generated|                     ; 41 (6)              ; 73 (23)                   ; 2048              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated                                                  ; dcfifo_a5q1                  ; work         ;
;                      |a_graycounter_8cc:wrptr_g1p|                 ; 11 (11)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_8cc:wrptr_g1p                      ; a_graycounter_8cc            ; work         ;
;                      |a_graycounter_du6:rdptr_g1p|                 ; 12 (12)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_du6:rdptr_g1p                      ; a_graycounter_du6            ; work         ;
;                      |alt_synch_pipe_0ol:rs_dgwp|                  ; 0 (0)               ; 14 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp                       ; alt_synch_pipe_0ol           ; work         ;
;                         |dffpipe_hd9:dffpipe12|                    ; 0 (0)               ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12 ; dffpipe_hd9                  ; work         ;
;                      |alt_synch_pipe_1ol:ws_dgrp|                  ; 0 (0)               ; 14 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp                       ; alt_synch_pipe_1ol           ; work         ;
;                         |dffpipe_id9:dffpipe15|                    ; 0 (0)               ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15 ; dffpipe_id9                  ; work         ;
;                      |altsyncram_qo91:fifo_ram|                    ; 0 (0)               ; 0 (0)                     ; 2048              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|altsyncram_qo91:fifo_ram                         ; altsyncram_qo91              ; work         ;
;                      |cmpr_vu5:rdempty_eq_comp|                    ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|cmpr_vu5:rdempty_eq_comp                         ; cmpr_vu5                     ; work         ;
;                      |cmpr_vu5:wrfull_eq_comp|                     ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|cmpr_vu5:wrfull_eq_comp                          ; cmpr_vu5                     ; work         ;
;                      |cntr_osd:cntr_b|                             ; 4 (4)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|cntr_osd:cntr_b                                  ; cntr_osd                     ; work         ;
;             |SER_UART_FIFO_TX32:C_FIFO_TX|                         ; 57 (0)              ; 83 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX                                                                                                                               ; SER_UART_FIFO_TX32           ; work         ;
;                |dcfifo_mixed_widths:dcfifo_mixed_widths_component| ; 57 (0)              ; 83 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component                                                                             ; dcfifo_mixed_widths          ; work         ;
;                   |dcfifo_8tq1:auto_generated|                     ; 57 (11)             ; 83 (21)                   ; 2048              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated                                                  ; dcfifo_8tq1                  ; work         ;
;                      |a_gray2bin_e9b:wrptr_g_gray2bin|             ; 6 (6)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_gray2bin_e9b:wrptr_g_gray2bin                  ; a_gray2bin_e9b               ; work         ;
;                      |a_gray2bin_e9b:ws_dgrp_gray2bin|             ; 6 (6)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_gray2bin_e9b:ws_dgrp_gray2bin                  ; a_gray2bin_e9b               ; work         ;
;                      |a_graycounter_9cc:wrptr_g1p|                 ; 11 (11)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_9cc:wrptr_g1p                      ; a_graycounter_9cc            ; work         ;
;                      |a_graycounter_cu6:rdptr_g1p|                 ; 11 (11)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_cu6:rdptr_g1p                      ; a_graycounter_cu6            ; work         ;
;                      |alt_synch_pipe_unl:rs_dgwp|                  ; 0 (0)               ; 14 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp                       ; alt_synch_pipe_unl           ; work         ;
;                         |dffpipe_fd9:dffpipe12|                    ; 0 (0)               ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12 ; dffpipe_fd9                  ; work         ;
;                      |alt_synch_pipe_vnl:ws_dgrp|                  ; 0 (0)               ; 14 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp                       ; alt_synch_pipe_vnl           ; work         ;
;                         |dffpipe_gd9:dffpipe16|                    ; 0 (0)               ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16 ; dffpipe_gd9                  ; work         ;
;                      |altsyncram_po91:fifo_ram|                    ; 0 (0)               ; 0 (0)                     ; 2048              ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|altsyncram_po91:fifo_ram                         ; altsyncram_po91              ; work         ;
;                      |cmpr_vu5:rdempty_eq_comp|                    ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|cmpr_vu5:rdempty_eq_comp                         ; cmpr_vu5                     ; work         ;
;                      |cmpr_vu5:wrfull_eq_comp|                     ; 3 (3)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|cmpr_vu5:wrfull_eq_comp                          ; cmpr_vu5                     ; work         ;
;                      |cntr_osd:cntr_b|                             ; 5 (5)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|cntr_osd:cntr_b                                  ; cntr_osd                     ; work         ;
;                      |dffpipe_ed9:ws_brp|                          ; 0 (0)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_brp                               ; dffpipe_ed9                  ; work         ;
;                      |dffpipe_ed9:ws_bwp|                          ; 0 (0)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_bwp                               ; dffpipe_ed9                  ; work         ;
;             |ser_uart:C_UART|                                      ; 57 (2)              ; 62 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART                                                                                                                                            ; ser_uart                     ; work         ;
;                |ser_uart_bdgen:\g_dbgen:C_BDGEN|                   ; 10 (10)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_bdgen:\g_dbgen:C_BDGEN                                                                                                            ; ser_uart_bdgen               ; work         ;
;                |ser_uart_deser:C_DESER|                            ; 21 (18)             ; 31 (28)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER                                                                                                                     ; ser_uart_deser               ; work         ;
;                   |ser_data_5_bits_filter:C_FILTER_SIN|            ; 3 (3)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|ser_data_5_bits_filter:C_FILTER_SIN                                                                                 ; ser_data_5_bits_filter       ; work         ;
;                |ser_uart_ser:C_SER|                                ; 24 (24)             ; 21 (21)                   ; 0                 ; 0          ; 0    ; 0            ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER                                                                                                                         ; ser_uart_ser                 ; work         ;
+--------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                                                           ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+------+
; Name                                                                                                                                                                                                                                ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size    ; MIF  ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+------+
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                              ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                              ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                              ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                              ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                              ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                              ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                              ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                              ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                            ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                            ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                            ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                            ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                            ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                            ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                            ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram|ALTSYNCRAM                                            ; AUTO ; Simple Dual Port ; 2048         ; 26           ; 2048         ; 26           ; 53248   ; None ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|ALTSYNCRAM                                                                                                                        ; AUTO ; Simple Dual Port ; 65536        ; 33           ; 65536        ; 33           ; 2162688 ; None ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|altsyncram_cia1:fifo_ram|ALTSYNCRAM                                                                          ; AUTO ; Simple Dual Port ; 64           ; 33           ; 64           ; 33           ; 2112    ; None ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|altsyncram_qo91:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 256          ; 8            ; 64           ; 32           ; 2048    ; None ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|altsyncram_po91:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64           ; 32           ; 256          ; 8            ; 2048    ; None ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                                 ;
+--------+--------------+---------+--------------+--------------+-----------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                                                                                                             ; IP Include File                                                         ;
+--------+--------------+---------+--------------+--------------+-----------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+
; Altera ; altera_pll   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL                                                                       ; src/PLL_MAIN.vhd                                                        ;
; Altera ; altera_pll   ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4                                                                        ; src/PLL_4K.vhd                                                          ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO                                                                                              ; src/FTR_L2_FIFO.vhd                                                     ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED                    ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED                    ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED                    ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED                    ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED                    ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED                    ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED                    ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED                    ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX                  ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX                  ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX                  ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX                  ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX                  ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX                  ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX                  ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX                  ; src/FTR_L1_FIFO.vhd                                                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX                                                ; ../../lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX ; ../../lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX ; ../../lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK                                      ; ../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
+--------+--------------+---------+--------------+--------------+-----------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|sl_int_detect_state[0]                                                         ;
+---------------------------------+---------------------------------+---------------------------------+------------------------------+
; Name                            ; sl_int_detect_state[0].STARTED1 ; sl_int_detect_state[0].STARTED0 ; sl_int_detect_state[0].RESET ;
+---------------------------------+---------------------------------+---------------------------------+------------------------------+
; sl_int_detect_state[0].RESET    ; 0                               ; 0                               ; 0                            ;
; sl_int_detect_state[0].STARTED0 ; 0                               ; 1                               ; 1                            ;
; sl_int_detect_state[0].STARTED1 ; 1                               ; 0                               ; 1                            ;
+---------------------------------+---------------------------------+---------------------------------+------------------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|sl_int_detect_state[1]                                                         ;
+---------------------------------+---------------------------------+---------------------------------+------------------------------+
; Name                            ; sl_int_detect_state[1].STARTED1 ; sl_int_detect_state[1].STARTED0 ; sl_int_detect_state[1].RESET ;
+---------------------------------+---------------------------------+---------------------------------+------------------------------+
; sl_int_detect_state[1].RESET    ; 0                               ; 0                               ; 0                            ;
; sl_int_detect_state[1].STARTED0 ; 0                               ; 1                               ; 1                            ;
; sl_int_detect_state[1].STARTED1 ; 1                               ; 0                               ; 1                            ;
+---------------------------------+---------------------------------+---------------------------------+------------------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_state                                                                                                                                                                                                                                                                                                                                                                         ;
+----------------------------------+------------------+----------------------------+------------------------+-------------------------+-------------------------+----------------------------------+---------------------------------+-------------------------+--------------------------+--------------------------+---------------------------+------------------------------+-----------------------+---------------------------------+-------------------------+-----------------------+-------------------+
; Name                             ; sl_int_state.ACK ; sl_int_state.SERIALIZE_CAL ; sl_int_state.SERIALIZE ; sl_int_state.SLOW_CMD_2 ; sl_int_state.SLOW_CMD_1 ; sl_int_state.SLOW_CMD_WRITE_MASK ; sl_int_state.SLOW_CMD_CAL_PULSE ; sl_int_state.LOOP_READY ; sl_int_state.RESET_READY ; sl_int_state.CHECK_READY ; sl_int_state.LOOP_RESTART ; sl_int_state.RESET_CAL_PULSE ; sl_int_state.SLOW_CMD ; sl_int_state.SOFT_RESET_DELAYED ; sl_int_state.SOFT_RESET ; sl_int_state.SOFT_L1A ; sl_int_state.IDLE ;
+----------------------------------+------------------+----------------------------+------------------------+-------------------------+-------------------------+----------------------------------+---------------------------------+-------------------------+--------------------------+--------------------------+---------------------------+------------------------------+-----------------------+---------------------------------+-------------------------+-----------------------+-------------------+
; sl_int_state.IDLE                ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 0                 ;
; sl_int_state.SOFT_L1A            ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 1                     ; 1                 ;
; sl_int_state.SOFT_RESET          ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 1                       ; 0                     ; 1                 ;
; sl_int_state.SOFT_RESET_DELAYED  ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 1                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD            ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 1                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.RESET_CAL_PULSE     ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 1                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.LOOP_RESTART        ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 1                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.CHECK_READY         ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 1                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.RESET_READY         ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 1                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.LOOP_READY          ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 1                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_CAL_PULSE  ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 1                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_WRITE_MASK ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 1                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_1          ; 0                ; 0                          ; 0                      ; 0                       ; 1                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_2          ; 0                ; 0                          ; 0                      ; 1                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SERIALIZE           ; 0                ; 0                          ; 1                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SERIALIZE_CAL       ; 0                ; 1                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.ACK                 ; 1                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
+----------------------------------+------------------+----------------------------+------------------------+-------------------------+-------------------------+----------------------------------+---------------------------------+-------------------------+--------------------------+--------------------------+---------------------------+------------------------------+-----------------------+---------------------------------+-------------------------+-----------------------+-------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_state                                                                                                                                                                                                                                                                                                                                                                         ;
+----------------------------------+------------------+----------------------------+------------------------+-------------------------+-------------------------+----------------------------------+---------------------------------+-------------------------+--------------------------+--------------------------+---------------------------+------------------------------+-----------------------+---------------------------------+-------------------------+-----------------------+-------------------+
; Name                             ; sl_int_state.ACK ; sl_int_state.SERIALIZE_CAL ; sl_int_state.SERIALIZE ; sl_int_state.SLOW_CMD_2 ; sl_int_state.SLOW_CMD_1 ; sl_int_state.SLOW_CMD_WRITE_MASK ; sl_int_state.SLOW_CMD_CAL_PULSE ; sl_int_state.LOOP_READY ; sl_int_state.RESET_READY ; sl_int_state.CHECK_READY ; sl_int_state.LOOP_RESTART ; sl_int_state.RESET_CAL_PULSE ; sl_int_state.SLOW_CMD ; sl_int_state.SOFT_RESET_DELAYED ; sl_int_state.SOFT_RESET ; sl_int_state.SOFT_L1A ; sl_int_state.IDLE ;
+----------------------------------+------------------+----------------------------+------------------------+-------------------------+-------------------------+----------------------------------+---------------------------------+-------------------------+--------------------------+--------------------------+---------------------------+------------------------------+-----------------------+---------------------------------+-------------------------+-----------------------+-------------------+
; sl_int_state.IDLE                ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 0                 ;
; sl_int_state.SOFT_L1A            ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 1                     ; 1                 ;
; sl_int_state.SOFT_RESET          ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 1                       ; 0                     ; 1                 ;
; sl_int_state.SOFT_RESET_DELAYED  ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 1                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD            ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 1                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.RESET_CAL_PULSE     ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 1                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.LOOP_RESTART        ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 1                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.CHECK_READY         ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 1                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.RESET_READY         ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 1                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.LOOP_READY          ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 1                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_CAL_PULSE  ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 1                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_WRITE_MASK ; 0                ; 0                          ; 0                      ; 0                       ; 0                       ; 1                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_1          ; 0                ; 0                          ; 0                      ; 0                       ; 1                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SLOW_CMD_2          ; 0                ; 0                          ; 0                      ; 1                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SERIALIZE           ; 0                ; 0                          ; 1                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.SERIALIZE_CAL       ; 0                ; 1                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
; sl_int_state.ACK                 ; 1                ; 0                          ; 0                      ; 0                       ; 0                       ; 0                                ; 0                               ; 0                       ; 0                        ; 0                        ; 0                         ; 0                            ; 0                     ; 0                               ; 0                       ; 0                     ; 1                 ;
+----------------------------------+------------------+----------------------------+------------------------+-------------------------+-------------------------+----------------------------------+---------------------------------+-------------------------+--------------------------+--------------------------+---------------------------+------------------------------+-----------------------+---------------------------------+-------------------------+-----------------------+-------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_state_ack                                                                            ;
+-------------------------------+-------------------------------+------------------------------+------------------------------+-----------------------+----------------------+---------------------------+
; Name                          ; sl_int_state_ack.WAIT_RESTART ; sl_int_state_ack.WAIT_ACK1_1 ; sl_int_state_ack.WAIT_ACK0_1 ; sl_int_state_ack.ACK2 ; sl_int_state_ack.ACK ; sl_int_state_ack.WAIT_ACK ;
+-------------------------------+-------------------------------+------------------------------+------------------------------+-----------------------+----------------------+---------------------------+
; sl_int_state_ack.WAIT_ACK     ; 0                             ; 0                            ; 0                            ; 0                     ; 0                    ; 0                         ;
; sl_int_state_ack.ACK          ; 0                             ; 0                            ; 0                            ; 0                     ; 1                    ; 1                         ;
; sl_int_state_ack.ACK2         ; 0                             ; 0                            ; 0                            ; 1                     ; 0                    ; 1                         ;
; sl_int_state_ack.WAIT_ACK0_1  ; 0                             ; 0                            ; 1                            ; 0                     ; 0                    ; 1                         ;
; sl_int_state_ack.WAIT_ACK1_1  ; 0                             ; 1                            ; 0                            ; 0                     ; 0                    ; 1                         ;
; sl_int_state_ack.WAIT_RESTART ; 1                             ; 0                            ; 0                            ; 0                     ; 0                    ; 1                         ;
+-------------------------------+-------------------------------+------------------------------+------------------------------+-----------------------+----------------------+---------------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_state[0]                                                                                                                                                                                                                      ;
+---------------------------------------+--------------------------------+---------------------------------------+-----------------------------------+------------------------------+----------------------------+---------------------+-----------------------+-------------------------------+---------------------------+----------------------+
; Name                                  ; sl_int_state[0].WAIT_COMMON_RQ ; sl_int_state[0].WAIT_END_BUSY_FROM_HW ; sl_int_state[0].WAIT_BUSY_FROM_HW ; sl_int_state[0].WAIT_RESTART ; sl_int_state[0].HARD_RESET ; sl_int_state[0].ACK ; sl_int_state[0].ERROR ; sl_int_state[0].WAIT_END_BUSY ; sl_int_state[0].WAIT_BUSY ; sl_int_state[0].IDLE ;
+---------------------------------------+--------------------------------+---------------------------------------+-----------------------------------+------------------------------+----------------------------+---------------------+-----------------------+-------------------------------+---------------------------+----------------------+
; sl_int_state[0].IDLE                  ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 0                    ;
; sl_int_state[0].WAIT_BUSY             ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 1                         ; 1                    ;
; sl_int_state[0].WAIT_END_BUSY         ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 1                             ; 0                         ; 1                    ;
; sl_int_state[0].ERROR                 ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 1                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[0].ACK                   ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 1                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[0].HARD_RESET            ; 0                              ; 0                                     ; 0                                 ; 0                            ; 1                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[0].WAIT_RESTART          ; 0                              ; 0                                     ; 0                                 ; 1                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[0].WAIT_BUSY_FROM_HW     ; 0                              ; 0                                     ; 1                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[0].WAIT_END_BUSY_FROM_HW ; 0                              ; 1                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[0].WAIT_COMMON_RQ        ; 1                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
+---------------------------------------+--------------------------------+---------------------------------------+-----------------------------------+------------------------------+----------------------------+---------------------+-----------------------+-------------------------------+---------------------------+----------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_state[1]                                                                                                                                                                                                                      ;
+---------------------------------------+--------------------------------+---------------------------------------+-----------------------------------+------------------------------+----------------------------+---------------------+-----------------------+-------------------------------+---------------------------+----------------------+
; Name                                  ; sl_int_state[1].WAIT_COMMON_RQ ; sl_int_state[1].WAIT_END_BUSY_FROM_HW ; sl_int_state[1].WAIT_BUSY_FROM_HW ; sl_int_state[1].WAIT_RESTART ; sl_int_state[1].HARD_RESET ; sl_int_state[1].ACK ; sl_int_state[1].ERROR ; sl_int_state[1].WAIT_END_BUSY ; sl_int_state[1].WAIT_BUSY ; sl_int_state[1].IDLE ;
+---------------------------------------+--------------------------------+---------------------------------------+-----------------------------------+------------------------------+----------------------------+---------------------+-----------------------+-------------------------------+---------------------------+----------------------+
; sl_int_state[1].IDLE                  ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 0                    ;
; sl_int_state[1].WAIT_BUSY             ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 1                         ; 1                    ;
; sl_int_state[1].WAIT_END_BUSY         ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 1                             ; 0                         ; 1                    ;
; sl_int_state[1].ERROR                 ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 1                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[1].ACK                   ; 0                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 1                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[1].HARD_RESET            ; 0                              ; 0                                     ; 0                                 ; 0                            ; 1                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[1].WAIT_RESTART          ; 0                              ; 0                                     ; 0                                 ; 1                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[1].WAIT_BUSY_FROM_HW     ; 0                              ; 0                                     ; 1                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[1].WAIT_END_BUSY_FROM_HW ; 0                              ; 1                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
; sl_int_state[1].WAIT_COMMON_RQ        ; 1                              ; 0                                     ; 0                                 ; 0                            ; 0                          ; 0                   ; 0                     ; 0                             ; 0                         ; 1                    ;
+---------------------------------------+--------------------------------+---------------------------------------+-----------------------------------+------------------------------+----------------------------+---------------------+-----------------------+-------------------------------+---------------------------+----------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX|sl_int_state                        ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED|sl_int_state                          ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; Name                       ; sl_int_state.TIMEOUT ; sl_int_state.OVERFLOW ; sl_int_state.WAIT_END ; sl_int_state.RECEIVING ; sl_int_state.WAIT_PREAMBLE ; sl_int_state.IDLE ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+
; sl_int_state.IDLE          ; 0                    ; 0                     ; 0                     ; 0                      ; 0                          ; 0                 ;
; sl_int_state.WAIT_PREAMBLE ; 0                    ; 0                     ; 0                     ; 0                      ; 1                          ; 1                 ;
; sl_int_state.RECEIVING     ; 0                    ; 0                     ; 0                     ; 1                      ; 0                          ; 1                 ;
; sl_int_state.WAIT_END      ; 0                    ; 0                     ; 1                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.OVERFLOW      ; 0                    ; 1                     ; 0                     ; 0                      ; 0                          ; 1                 ;
; sl_int_state.TIMEOUT       ; 1                    ; 0                     ; 0                     ; 0                      ; 0                          ; 1                 ;
+----------------------------+----------------------+-----------------------+-----------------------+------------------------+----------------------------+-------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_mux                                                                                                                                                                                                                                                                 ;
+----------------------------------------+----------------------------------------+-----------------+------------------------+-------------------------+-------------------------------+---------------------------------+---------------------------------+--------------------------+-----------------------+------------------+-----------------+
; Name                                   ; sl_int_mux.TRB_DATA_L1A_FIFO_NOT_EMPTY ; sl_int_mux.STOP ; sl_int_mux.TRB_TRAILER ; sl_int_mux.READ_L1_FIFO ; sl_int_mux.TRB_DATA_FIFO_FULL ; sl_int_mux.TRB_DATA_TIMEOUT_END ; sl_int_mux.TRB_DATA_TIMEOUT_L1A ; sl_int_mux.TRB_DATA_BCID ; sl_int_mux.TRB_HEADER ; sl_int_mux.START ; sl_int_mux.NONE ;
+----------------------------------------+----------------------------------------+-----------------+------------------------+-------------------------+-------------------------------+---------------------------------+---------------------------------+--------------------------+-----------------------+------------------+-----------------+
; sl_int_mux.NONE                        ; 0                                      ; 0               ; 0                      ; 0                       ; 0                             ; 0                               ; 0                               ; 0                        ; 0                     ; 0                ; 0               ;
; sl_int_mux.START                       ; 0                                      ; 0               ; 0                      ; 0                       ; 0                             ; 0                               ; 0                               ; 0                        ; 0                     ; 1                ; 1               ;
; sl_int_mux.TRB_HEADER                  ; 0                                      ; 0               ; 0                      ; 0                       ; 0                             ; 0                               ; 0                               ; 0                        ; 1                     ; 0                ; 1               ;
; sl_int_mux.TRB_DATA_BCID               ; 0                                      ; 0               ; 0                      ; 0                       ; 0                             ; 0                               ; 0                               ; 1                        ; 0                     ; 0                ; 1               ;
; sl_int_mux.TRB_DATA_TIMEOUT_L1A        ; 0                                      ; 0               ; 0                      ; 0                       ; 0                             ; 0                               ; 1                               ; 0                        ; 0                     ; 0                ; 1               ;
; sl_int_mux.TRB_DATA_TIMEOUT_END        ; 0                                      ; 0               ; 0                      ; 0                       ; 0                             ; 1                               ; 0                               ; 0                        ; 0                     ; 0                ; 1               ;
; sl_int_mux.TRB_DATA_FIFO_FULL          ; 0                                      ; 0               ; 0                      ; 0                       ; 1                             ; 0                               ; 0                               ; 0                        ; 0                     ; 0                ; 1               ;
; sl_int_mux.READ_L1_FIFO                ; 0                                      ; 0               ; 0                      ; 1                       ; 0                             ; 0                               ; 0                               ; 0                        ; 0                     ; 0                ; 1               ;
; sl_int_mux.TRB_TRAILER                 ; 0                                      ; 0               ; 1                      ; 0                       ; 0                             ; 0                               ; 0                               ; 0                        ; 0                     ; 0                ; 1               ;
; sl_int_mux.STOP                        ; 0                                      ; 1               ; 0                      ; 0                       ; 0                             ; 0                               ; 0                               ; 0                        ; 0                     ; 0                ; 1               ;
; sl_int_mux.TRB_DATA_L1A_FIFO_NOT_EMPTY ; 1                                      ; 0               ; 0                      ; 0                       ; 0                             ; 0                               ; 0                               ; 0                        ; 0                     ; 0                ; 1               ;
+----------------------------------------+----------------------------------------+-----------------+------------------------+-------------------------+-------------------------------+---------------------------------+---------------------------------+--------------------------+-----------------------+------------------+-----------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_timeout_state                             ;
+------------------------------+------------------------------+------------------------------+---------------------------+
; Name                         ; sl_int_timeout_state.STARTED ; sl_int_timeout_state.TIMEOUT ; sl_int_timeout_state.NONE ;
+------------------------------+------------------------------+------------------------------+---------------------------+
; sl_int_timeout_state.NONE    ; 0                            ; 0                            ; 0                         ;
; sl_int_timeout_state.TIMEOUT ; 0                            ; 1                            ; 1                         ;
; sl_int_timeout_state.STARTED ; 1                            ; 0                            ; 1                         ;
+------------------------------+------------------------------+------------------------------+---------------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_L1A_state                                 ;
+--------------------------------+--------------------------------+------------------------+-----------------------------+
; Name                           ; sl_int_L1A_state.WAIT_NO_PULSE ; sl_int_L1A_state.COUNT ; sl_int_L1A_state.WAIT_PULSE ;
+--------------------------------+--------------------------------+------------------------+-----------------------------+
; sl_int_L1A_state.WAIT_PULSE    ; 0                              ; 0                      ; 0                           ;
; sl_int_L1A_state.COUNT         ; 0                              ; 1                      ; 1                           ;
; sl_int_L1A_state.WAIT_NO_PULSE ; 1                              ; 0                      ; 1                           ;
+--------------------------------+--------------------------------+------------------------+-----------------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_state                                                                                                                                                                                                                                                                       ;
+-----------------------------------+-------------------+--------------------------+-------------------------------+---------------------------+---------------------------------+-----------------------------------+-----------------------------------+----------------------------+-------------------------+----------------------+-------------------+
; Name                              ; sl_int_state.STOP ; sl_int_state.TRB_TRAILER ; sl_int_state.TRB_TRAILER_WAIT ; sl_int_state.READ_L1_FIFO ; sl_int_state.TRB_DATA_FIFO_FULL ; sl_int_state.TRB_DATA_TIMEOUT_END ; sl_int_state.TRB_DATA_TIMEOUT_L1A ; sl_int_state.TRB_DATA_BCID ; sl_int_state.TRB_HEADER ; sl_int_state.RECEIVE ; sl_int_state.IDLE ;
+-----------------------------------+-------------------+--------------------------+-------------------------------+---------------------------+---------------------------------+-----------------------------------+-----------------------------------+----------------------------+-------------------------+----------------------+-------------------+
; sl_int_state.IDLE                 ; 0                 ; 0                        ; 0                             ; 0                         ; 0                               ; 0                                 ; 0                                 ; 0                          ; 0                       ; 0                    ; 0                 ;
; sl_int_state.RECEIVE              ; 0                 ; 0                        ; 0                             ; 0                         ; 0                               ; 0                                 ; 0                                 ; 0                          ; 0                       ; 1                    ; 1                 ;
; sl_int_state.TRB_HEADER           ; 0                 ; 0                        ; 0                             ; 0                         ; 0                               ; 0                                 ; 0                                 ; 0                          ; 1                       ; 0                    ; 1                 ;
; sl_int_state.TRB_DATA_BCID        ; 0                 ; 0                        ; 0                             ; 0                         ; 0                               ; 0                                 ; 0                                 ; 1                          ; 0                       ; 0                    ; 1                 ;
; sl_int_state.TRB_DATA_TIMEOUT_L1A ; 0                 ; 0                        ; 0                             ; 0                         ; 0                               ; 0                                 ; 1                                 ; 0                          ; 0                       ; 0                    ; 1                 ;
; sl_int_state.TRB_DATA_TIMEOUT_END ; 0                 ; 0                        ; 0                             ; 0                         ; 0                               ; 1                                 ; 0                                 ; 0                          ; 0                       ; 0                    ; 1                 ;
; sl_int_state.TRB_DATA_FIFO_FULL   ; 0                 ; 0                        ; 0                             ; 0                         ; 1                               ; 0                                 ; 0                                 ; 0                          ; 0                       ; 0                    ; 1                 ;
; sl_int_state.READ_L1_FIFO         ; 0                 ; 0                        ; 0                             ; 1                         ; 0                               ; 0                                 ; 0                                 ; 0                          ; 0                       ; 0                    ; 1                 ;
; sl_int_state.TRB_TRAILER_WAIT     ; 0                 ; 0                        ; 1                             ; 0                         ; 0                               ; 0                                 ; 0                                 ; 0                          ; 0                       ; 0                    ; 1                 ;
; sl_int_state.TRB_TRAILER          ; 0                 ; 1                        ; 0                             ; 0                         ; 0                               ; 0                                 ; 0                                 ; 0                          ; 0                       ; 0                    ; 1                 ;
; sl_int_state.STOP                 ; 1                 ; 0                        ; 0                             ; 0                         ; 0                               ; 0                                 ; 0                                 ; 0                          ; 0                       ; 0                    ; 1                 ;
+-----------------------------------+-------------------+--------------------------+-------------------------------+---------------------------+---------------------------------+-----------------------------------+-----------------------------------+----------------------------+-------------------------+----------------------+-------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_state ;
+--------------------+------------------+------------------+--------------------+----------------------+
; Name               ; sl_int_state.ERR ; sl_int_state.ACK ; sl_int_state.STORE ; sl_int_state.IDLE    ;
+--------------------+------------------+------------------+--------------------+----------------------+
; sl_int_state.IDLE  ; 0                ; 0                ; 0                  ; 0                    ;
; sl_int_state.STORE ; 0                ; 0                ; 1                  ; 1                    ;
; sl_int_state.ACK   ; 0                ; 1                ; 0                  ; 1                    ;
; sl_int_state.ERR   ; 1                ; 0                ; 0                  ; 1                    ;
+--------------------+------------------+------------------+--------------------+----------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET|sl_int_state ;
+--------------------+------------------+--------------------+-----------------------------------------+
; Name               ; sl_int_state.ACK ; sl_int_state.LATCH ; sl_int_state.IDLE                       ;
+--------------------+------------------+--------------------+-----------------------------------------+
; sl_int_state.IDLE  ; 0                ; 0                  ; 0                                       ;
; sl_int_state.LATCH ; 0                ; 1                  ; 1                                       ;
; sl_int_state.ACK   ; 1                ; 0                  ; 1                                       ;
+--------------------+------------------+--------------------+-----------------------------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_state ;
+--------------------+------------------+------------------+--------------------+----------------------+
; Name               ; sl_int_state.ERR ; sl_int_state.ACK ; sl_int_state.STORE ; sl_int_state.IDLE    ;
+--------------------+------------------+------------------+--------------------+----------------------+
; sl_int_state.IDLE  ; 0                ; 0                ; 0                  ; 0                    ;
; sl_int_state.STORE ; 0                ; 0                ; 1                  ; 1                    ;
; sl_int_state.ACK   ; 0                ; 1                ; 0                  ; 1                    ;
; sl_int_state.ERR   ; 1                ; 0                ; 0                  ; 1                    ;
+--------------------+------------------+------------------+--------------------+----------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET|sl_int_state ;
+--------------------+------------------+--------------------+---------------------------------------+
; Name               ; sl_int_state.ACK ; sl_int_state.LATCH ; sl_int_state.IDLE                     ;
+--------------------+------------------+--------------------+---------------------------------------+
; sl_int_state.IDLE  ; 0                ; 0                  ; 0                                     ;
; sl_int_state.LATCH ; 0                ; 1                  ; 1                                     ;
; sl_int_state.ACK   ; 1                ; 0                  ; 1                                     ;
+--------------------+------------------+--------------------+---------------------------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_state ;
+--------------------+------------------+------------------+--------------------+--------------------+
; Name               ; sl_int_state.ERR ; sl_int_state.ACK ; sl_int_state.STORE ; sl_int_state.IDLE  ;
+--------------------+------------------+------------------+--------------------+--------------------+
; sl_int_state.IDLE  ; 0                ; 0                ; 0                  ; 0                  ;
; sl_int_state.STORE ; 0                ; 0                ; 1                  ; 1                  ;
; sl_int_state.ACK   ; 0                ; 1                ; 0                  ; 1                  ;
; sl_int_state.ERR   ; 1                ; 0                ; 0                  ; 1                  ;
+--------------------+------------------+------------------+--------------------+--------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET|sl_int_state ;
+--------------------+------------------+--------------------+--------------------------------------+
; Name               ; sl_int_state.ACK ; sl_int_state.LATCH ; sl_int_state.IDLE                    ;
+--------------------+------------------+--------------------+--------------------------------------+
; sl_int_state.IDLE  ; 0                ; 0                  ; 0                                    ;
; sl_int_state.LATCH ; 0                ; 1                  ; 1                                    ;
; sl_int_state.ACK   ; 1                ; 0                  ; 1                                    ;
+--------------------+------------------+--------------------+--------------------------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_state ;
+--------------------+------------------+------------------+--------------------+-------------------+
; Name               ; sl_int_state.ERR ; sl_int_state.ACK ; sl_int_state.STORE ; sl_int_state.IDLE ;
+--------------------+------------------+------------------+--------------------+-------------------+
; sl_int_state.IDLE  ; 0                ; 0                ; 0                  ; 0                 ;
; sl_int_state.STORE ; 0                ; 0                ; 1                  ; 1                 ;
; sl_int_state.ACK   ; 0                ; 1                ; 0                  ; 1                 ;
; sl_int_state.ERR   ; 1                ; 0                ; 0                  ; 1                 ;
+--------------------+------------------+------------------+--------------------+-------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|sl_int_state ;
+-------------------------+------------------------+----------------------+----------------------+-------------------------------------------------------------------+
; Name                    ; sl_int_state.WAIT_STOP ; sl_int_state.DATA_AV ; sl_int_state.RECEIVE ; sl_int_state.WAIT_START                                           ;
+-------------------------+------------------------+----------------------+----------------------+-------------------------------------------------------------------+
; sl_int_state.WAIT_START ; 0                      ; 0                    ; 0                    ; 0                                                                 ;
; sl_int_state.RECEIVE    ; 0                      ; 0                    ; 1                    ; 1                                                                 ;
; sl_int_state.DATA_AV    ; 0                      ; 1                    ; 0                    ; 1                                                                 ;
; sl_int_state.WAIT_STOP  ; 1                      ; 0                    ; 0                    ; 1                                                                 ;
+-------------------------+------------------------+----------------------+----------------------+-------------------------------------------------------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER|sl_int_state ;
+-------------------------+-------------------+---------------------+-----------------------+--------------------+--------------------+--------------------------+
; Name                    ; sl_int_state.STOP ; sl_int_state.PARITY ; sl_int_state.TRANSMIT ; sl_int_state.START ; sl_int_state.LATCH ; sl_int_state.WAIT_START  ;
+-------------------------+-------------------+---------------------+-----------------------+--------------------+--------------------+--------------------------+
; sl_int_state.WAIT_START ; 0                 ; 0                   ; 0                     ; 0                  ; 0                  ; 0                        ;
; sl_int_state.LATCH      ; 0                 ; 0                   ; 0                     ; 0                  ; 1                  ; 1                        ;
; sl_int_state.START      ; 0                 ; 0                   ; 0                     ; 1                  ; 0                  ; 1                        ;
; sl_int_state.TRANSMIT   ; 0                 ; 0                   ; 1                     ; 0                  ; 0                  ; 1                        ;
; sl_int_state.PARITY     ; 0                 ; 1                   ; 0                     ; 0                  ; 0                  ; 1                        ;
; sl_int_state.STOP       ; 1                 ; 0                   ; 0                     ; 0                  ; 0                  ; 1                        ;
+-------------------------+-------------------+---------------------+-----------------------+--------------------+--------------------+--------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_timeout_state                ;
+------------------------------+------------------------------+----------------------------+----------------------------+
; Name                         ; sl_int_timeout_state.TIMEOUT ; sl_int_timeout_state.COUNT ; sl_int_timeout_state.RESET ;
+------------------------------+------------------------------+----------------------------+----------------------------+
; sl_int_timeout_state.RESET   ; 0                            ; 0                          ; 0                          ;
; sl_int_timeout_state.COUNT   ; 0                            ; 1                          ; 1                          ;
; sl_int_timeout_state.TIMEOUT ; 1                            ; 0                          ; 1                          ;
+------------------------------+------------------------------+----------------------------+----------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_process_state                                                                                                                                                                                                                                                                            ;
+-----------------------------------------+--------------------------+---------------------------------------+-----------------------------------+---------------------------------------+-----------------------------------+-----------------------------------------+----------------------------------------+---------------------------------------+---------------------------+
; Name                                    ; sl_int_process_state.ACK ; sl_int_process_state.SET_USER_SET_CMD ; sl_int_process_state.SET_USER_SET ; sl_int_process_state.APPLY_CONFIG_END ; sl_int_process_state.APPLY_CONFIG ; sl_int_process_state.APPLY_CONFIG_START ; sl_int_process_state.SET_READOUT_PARAM ; sl_int_process_state.SET_DIRECT_PARAM ; sl_int_process_state.IDLE ;
+-----------------------------------------+--------------------------+---------------------------------------+-----------------------------------+---------------------------------------+-----------------------------------+-----------------------------------------+----------------------------------------+---------------------------------------+---------------------------+
; sl_int_process_state.IDLE               ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 0                         ;
; sl_int_process_state.SET_DIRECT_PARAM   ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 1                                     ; 1                         ;
; sl_int_process_state.SET_READOUT_PARAM  ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 1                                      ; 0                                     ; 1                         ;
; sl_int_process_state.APPLY_CONFIG_START ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 1                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.APPLY_CONFIG       ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 1                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.APPLY_CONFIG_END   ; 0                        ; 0                                     ; 0                                 ; 1                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.SET_USER_SET       ; 0                        ; 0                                     ; 1                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.SET_USER_SET_CMD   ; 0                        ; 1                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.ACK                ; 1                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
+-----------------------------------------+--------------------------+---------------------------------------+-----------------------------------+---------------------------------------+-----------------------------------+-----------------------------------------+----------------------------------------+---------------------------------------+---------------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------------+-------------------------------------+-------------------------------+--------------------------------------+-----------------------------------------------+--------------------------+-------------------------+--------------------------------------+------------------------+--------------------------------------+---------------------------------------+-----------------------------------------+-----------------------------------------+-----------------------------------+-----------------------------------+-------------------------------------+-------------------------------+-------------------------------+-------------------------+-------------------------+--------------------------------+-----------------+-------------------+
; Name                                          ; sl_int_state.CMD_2FRM_PROCESS_DELAY ; sl_int_state.CMD_DECODE_DELAY ; sl_int_state.CMD_NOT_ADRRESSED_DELAY ; sl_int_state.CMD_SET_CONFIG_CMD_PROCESS_DELAY ; sl_int_state.CHECK_VALID ; sl_int_state.CMD_ANSWER ; sl_int_state.WAIT_FIFO_PROCESS_DELAY ; sl_int_state.WAIT_FIFO ; sl_int_state.CMD_SET_CONFIG_WAIT_CRC ; sl_int_state.CMD_SET_CONFIG_START_CRC ; sl_int_state.CMD_SET_CONFIG_ARG_PROCESS ; sl_int_state.CMD_SET_CONFIG_CMD_PROCESS ; sl_int_state.CMD_SET_CONFIG_VALID ; sl_int_state.CMD_2FRM_PROCESS_END ; sl_int_state.CMD_2FRM_PROCESS_CHECK ; sl_int_state.CMD_2FRM_PROCESS ; sl_int_state.CMD_1FRM_PROCESS ; sl_int_state.CMD_DECODE ; sl_int_state.ADD_DECODE ; sl_int_state.CMD_NOT_ADRRESSED ; sl_int_state.RD ; sl_int_state.IDLE ;
+-----------------------------------------------+-------------------------------------+-------------------------------+--------------------------------------+-----------------------------------------------+--------------------------+-------------------------+--------------------------------------+------------------------+--------------------------------------+---------------------------------------+-----------------------------------------+-----------------------------------------+-----------------------------------+-----------------------------------+-------------------------------------+-------------------------------+-------------------------------+-------------------------+-------------------------+--------------------------------+-----------------+-------------------+
; sl_int_state.IDLE                             ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 0                 ;
; sl_int_state.RD                               ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 1               ; 1                 ;
; sl_int_state.CMD_NOT_ADRRESSED                ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 1                              ; 0               ; 1                 ;
; sl_int_state.ADD_DECODE                       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 1                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_DECODE                       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 1                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_1FRM_PROCESS                 ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 1                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_2FRM_PROCESS                 ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 1                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_2FRM_PROCESS_CHECK           ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 1                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_2FRM_PROCESS_END             ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 1                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_VALID             ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 1                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_CMD_PROCESS       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 1                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_ARG_PROCESS       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 1                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_START_CRC         ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 1                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_WAIT_CRC          ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 1                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.WAIT_FIFO                        ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 1                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.WAIT_FIFO_PROCESS_DELAY          ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 1                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_ANSWER                       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 1                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CHECK_VALID                      ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 1                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_CMD_PROCESS_DELAY ; 0                                   ; 0                             ; 0                                    ; 1                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_NOT_ADRRESSED_DELAY          ; 0                                   ; 0                             ; 1                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_DECODE_DELAY                 ; 0                                   ; 1                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_2FRM_PROCESS_DELAY           ; 1                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
+-----------------------------------------------+-------------------------------------+-------------------------------+--------------------------------------+-----------------------------------------------+--------------------------+-------------------------+--------------------------------------+------------------------+--------------------------------------+---------------------------------------+-----------------------------------------+-----------------------------------------+-----------------------------------+-----------------------------------+-------------------------------------+-------------------------------+-------------------------------+-------------------------+-------------------------+--------------------------------+-----------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_timeout_state           ;
+------------------------------+------------------------------+----------------------------+----------------------------+
; Name                         ; sl_int_timeout_state.TIMEOUT ; sl_int_timeout_state.COUNT ; sl_int_timeout_state.RESET ;
+------------------------------+------------------------------+----------------------------+----------------------------+
; sl_int_timeout_state.RESET   ; 0                            ; 0                          ; 0                          ;
; sl_int_timeout_state.COUNT   ; 0                            ; 1                          ; 1                          ;
; sl_int_timeout_state.TIMEOUT ; 1                            ; 0                          ; 1                          ;
+------------------------------+------------------------------+----------------------------+----------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+----------------------------------------------+----------------------------------------------+-----------------------------------+-----------------------+------------------+-----------------+--------------------------------+---------------------+-----------------------------+----------------------------------------+----------------------------------+-----------------------------------+-----------------------------+---------------------------+--------------------------+-------------------------+-------------------+
; Name                                         ; sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY ; sl_int_state.GET_CONFIG_CMD_DELAY ; sl_int_state.WR_DELAY ; sl_int_state.ACK ; sl_int_state.WR ; sl_int_state.GET_USER_CMD_WAIT ; sl_int_state.ANSWER ; sl_int_state.GET_CONFIG_END ; sl_int_state.GET_CONFIG_ARG_CHECK_FIFO ; sl_int_state.GET_CONFIG_WAIT_CRC ; sl_int_state.GET_CONFIG_START_CRC ; sl_int_state.GET_CONFIG_CMD ; sl_int_state.GET_BOARD_ID ; sl_int_state.READ_STATUS ; sl_int_state.FW_VERSION ; sl_int_state.IDLE ;
+----------------------------------------------+----------------------------------------------+-----------------------------------+-----------------------+------------------+-----------------+--------------------------------+---------------------+-----------------------------+----------------------------------------+----------------------------------+-----------------------------------+-----------------------------+---------------------------+--------------------------+-------------------------+-------------------+
; sl_int_state.IDLE                            ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 0                 ;
; sl_int_state.FW_VERSION                      ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 1                       ; 1                 ;
; sl_int_state.READ_STATUS                     ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 1                        ; 0                       ; 1                 ;
; sl_int_state.GET_BOARD_ID                    ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 1                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_CMD                  ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 1                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_START_CRC            ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 1                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_WAIT_CRC             ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 1                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_ARG_CHECK_FIFO       ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 1                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_END                  ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 1                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.ANSWER                          ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 1                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_USER_CMD_WAIT               ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 1                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.WR                              ; 0                                            ; 0                                 ; 0                     ; 0                ; 1               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.ACK                             ; 0                                            ; 0                                 ; 0                     ; 1                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.WR_DELAY                        ; 0                                            ; 0                                 ; 1                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_CMD_DELAY            ; 0                                            ; 1                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY ; 1                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
+----------------------------------------------+----------------------------------------------+-----------------------------------+-----------------------+------------------+-----------------+--------------------------------+---------------------+-----------------------------+----------------------------------------+----------------------------------+-----------------------------------+-----------------------------+---------------------------+--------------------------+-------------------------+-------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_state ;
+-------------------------+---------------------+----------------------+----------------------------------------------------+
; Name                    ; sl_int_state.CRC_AV ; sl_int_state.COMPUTE ; sl_int_state.WAIT_START                            ;
+-------------------------+---------------------+----------------------+----------------------------------------------------+
; sl_int_state.WAIT_START ; 0                   ; 0                    ; 0                                                  ;
; sl_int_state.COMPUTE    ; 0                   ; 1                    ; 1                                                  ;
; sl_int_state.CRC_AV     ; 1                   ; 0                    ; 1                                                  ;
+-------------------------+---------------------+----------------------+----------------------------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_state                                                                ;
+---------------------------+---------------------------+------------------------+------------------+-----------------+-------------------+--------------------+
; Name                      ; sl_int_state.WAIT_UC_FULL ; sl_int_state.CHECK_ZLP ; sl_int_state.ZLP ; sl_int_state.WR ; sl_int_state.IDLE ; sl_int_state.START ;
+---------------------------+---------------------------+------------------------+------------------+-----------------+-------------------+--------------------+
; sl_int_state.START        ; 0                         ; 0                      ; 0                ; 0               ; 0                 ; 0                  ;
; sl_int_state.IDLE         ; 0                         ; 0                      ; 0                ; 0               ; 1                 ; 1                  ;
; sl_int_state.WR           ; 0                         ; 0                      ; 0                ; 1               ; 0                 ; 1                  ;
; sl_int_state.ZLP          ; 0                         ; 0                      ; 1                ; 0               ; 0                 ; 1                  ;
; sl_int_state.CHECK_ZLP    ; 0                         ; 1                      ; 0                ; 0               ; 0                 ; 1                  ;
; sl_int_state.WAIT_UC_FULL ; 1                         ; 0                      ; 0                ; 0               ; 0                 ; 1                  ;
+---------------------------+---------------------------+------------------------+------------------+-----------------+-------------------+--------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_start_state                                                                                                ;
+----------------------------+----------------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------------+
; Name                       ; sl_int_start_state.STARTED ; sl_int_start_state.START4 ; sl_int_start_state.START3 ; sl_int_start_state.START2 ; sl_int_start_state.START1 ; sl_int_start_state.START ;
+----------------------------+----------------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------------+
; sl_int_start_state.START   ; 0                          ; 0                         ; 0                         ; 0                         ; 0                         ; 0                        ;
; sl_int_start_state.START1  ; 0                          ; 0                         ; 0                         ; 0                         ; 1                         ; 1                        ;
; sl_int_start_state.START2  ; 0                          ; 0                         ; 0                         ; 1                         ; 0                         ; 1                        ;
; sl_int_start_state.START3  ; 0                          ; 0                         ; 1                         ; 0                         ; 0                         ; 1                        ;
; sl_int_start_state.START4  ; 0                          ; 1                         ; 0                         ; 0                         ; 0                         ; 1                        ;
; sl_int_start_state.STARTED ; 1                          ; 0                         ; 0                         ; 0                         ; 0                         ; 1                        ;
+----------------------------+----------------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|sl_int_state                                                                                                      ;
+-----------------------------+---------------------+--------------------+-----------------------------+--------------------------+--------------------+-------------------+
; Name                        ; sl_int_state.CLEAR2 ; sl_int_state.CLEAR ; sl_int_state.FORCED_INT_CLK ; sl_int_state.WAIT_LOCKED ; sl_int_state.RESET ; sl_int_state.IDLE ;
+-----------------------------+---------------------+--------------------+-----------------------------+--------------------------+--------------------+-------------------+
; sl_int_state.IDLE           ; 0                   ; 0                  ; 0                           ; 0                        ; 0                  ; 0                 ;
; sl_int_state.RESET          ; 0                   ; 0                  ; 0                           ; 0                        ; 1                  ; 1                 ;
; sl_int_state.WAIT_LOCKED    ; 0                   ; 0                  ; 0                           ; 1                        ; 0                  ; 1                 ;
; sl_int_state.FORCED_INT_CLK ; 0                   ; 0                  ; 1                           ; 0                        ; 0                  ; 1                 ;
; sl_int_state.CLEAR          ; 0                   ; 1                  ; 0                           ; 0                        ; 0                  ; 1                 ;
; sl_int_state.CLEAR2         ; 1                   ; 0                  ; 0                           ; 0                        ; 0                  ; 1                 ;
+-----------------------------+---------------------+--------------------+-----------------------------+--------------------------+--------------------+-------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE|sl_int_state                                                                                  ;
+------------------------------+------------------------+------------------------+------------------------+------------------------------+------------------------+-------------------+
; Name                         ; sl_int_state.PHASE_EN1 ; sl_int_state.PHASE_EN0 ; sl_int_state.PHASE_DIS ; sl_int_state.PLL_WAIT_LOCKED ; sl_int_state.PLL_RESET ; sl_int_state.IDLE ;
+------------------------------+------------------------+------------------------+------------------------+------------------------------+------------------------+-------------------+
; sl_int_state.IDLE            ; 0                      ; 0                      ; 0                      ; 0                            ; 0                      ; 0                 ;
; sl_int_state.PLL_RESET       ; 0                      ; 0                      ; 0                      ; 0                            ; 1                      ; 1                 ;
; sl_int_state.PLL_WAIT_LOCKED ; 0                      ; 0                      ; 0                      ; 1                            ; 0                      ; 1                 ;
; sl_int_state.PHASE_DIS       ; 0                      ; 0                      ; 1                      ; 0                            ; 0                      ; 1                 ;
; sl_int_state.PHASE_EN0       ; 0                      ; 1                      ; 0                      ; 0                            ; 0                      ; 1                 ;
; sl_int_state.PHASE_EN1       ; 1                      ; 0                      ; 0                      ; 0                            ; 0                      ; 1                 ;
+------------------------------+------------------------+------------------------+------------------------+------------------------------+------------------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state                                                                                            ;
+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+-----------------------------------+
; Name                               ; dps_current_state.PHASE_DONE_LOW_0 ; dps_current_state.PHASE_DONE_LOW_4 ; dps_current_state.PHASE_DONE_LOW_3 ; dps_current_state.PHASE_DONE_LOW_2 ; dps_current_state.PHASE_DONE_LOW_1 ; dps_current_state.PHASE_DONE_HIGH ;
+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+-----------------------------------+
; dps_current_state.PHASE_DONE_HIGH  ; 0                                  ; 0                                  ; 0                                  ; 0                                  ; 0                                  ; 0                                 ;
; dps_current_state.PHASE_DONE_LOW_1 ; 0                                  ; 0                                  ; 0                                  ; 0                                  ; 1                                  ; 1                                 ;
; dps_current_state.PHASE_DONE_LOW_2 ; 0                                  ; 0                                  ; 0                                  ; 1                                  ; 0                                  ; 1                                 ;
; dps_current_state.PHASE_DONE_LOW_3 ; 0                                  ; 0                                  ; 1                                  ; 0                                  ; 0                                  ; 1                                 ;
; dps_current_state.PHASE_DONE_LOW_4 ; 0                                  ; 1                                  ; 0                                  ; 0                                  ; 0                                  ; 1                                 ;
; dps_current_state.PHASE_DONE_LOW_0 ; 1                                  ; 0                                  ; 0                                  ; 0                                  ; 0                                  ; 1                                 ;
+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+-----------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name                                                                                                                                                                                                                                               ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][5]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][7]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][4]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][6]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][9]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][11]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][8]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][10]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][0]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][8]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe17a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe17a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe17a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe17a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe17a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe17a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe17a[1] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe14a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe14a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe14a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe14a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe14a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe14a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe14a[1] ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[16]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[14]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[15]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[12]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[13]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[10]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[11]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[8]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[9]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[6]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[7]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[4]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[5]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[2]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[3]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[0]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe20a[1]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe15a[1]                                            ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe15a[6]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe15a[4]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe15a[5]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe15a[2]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe15a[3]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe15a[0]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe15a[1]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe18a[6]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe18a[4]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe18a[5]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe18a[2]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe18a[3]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe18a[0]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe18a[1]                                                                          ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][4]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][0]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][6]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][2]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][8]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][7]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][3]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][5]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[1][1]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][2]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][10]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][0]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][1]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][2]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][3]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][4]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][5]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][6]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][7]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][8]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][9]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][10]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[2][11]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][0]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][1]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][2]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][3]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][3]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][11]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][1]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[0][9]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][7]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][6]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][5]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][4]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][0]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][1]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][2]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][3]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe16a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe16a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe16a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe16a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe16a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe16a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe16a[1] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a[1] ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][0]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][12]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][6]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][3]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][1]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][13]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][7]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][4]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][2]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][14]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][8]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][5]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][3]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][0]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][9]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][6]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][4]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][1]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][10]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][7]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][5]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][2]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[0][11]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][8]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[16]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[14]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[15]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[12]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[13]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[10]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[11]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[8]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[9]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[6]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[7]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[4]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[5]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[2]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[3]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[0]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18|dffe19a[1]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13|dffe14a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][0]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][11]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][10]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][9]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][8]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][7]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][6]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][5]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][4]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][3]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][2]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][1]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[7][0]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][11]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][10]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][9]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][8]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][7]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][6]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][5]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe14a[6]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe14a[4]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe14a[5]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe14a[2]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe14a[3]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe14a[0]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe14a[1]                                                                          ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[16]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[14]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[15]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[12]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[13]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[10]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[11]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[8]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[9]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[6]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[7]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[4]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[5]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[2]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[3]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[0]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe17a[1]                                                                                                                        ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe17a[6]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe17a[4]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe17a[5]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe17a[2]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe17a[3]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe17a[0]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe17a[1]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe14a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe14a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe14a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe14a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe14a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe14a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe14a[1] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe18a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe18a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe18a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe18a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe18a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe18a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe18a[1] ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][7]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][6]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][5]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][4]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][3]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][2]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][1]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][0]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][9]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][10]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[5][11]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][0]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][11]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][10]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][9]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][8]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][7]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][6]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][5]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][4]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][3]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][2]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[8][1]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][0]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][7]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][6]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][5]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][4]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][3]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][2]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][11]                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][6]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][9]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][10]                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][11]                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][0]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][9]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][6]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][2]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][3]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][7]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][4]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][5]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][4]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][7]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][5]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][9]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][10]                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][11]                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][0]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][1]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][2]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][3]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][6]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][4]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][5]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][7]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][8]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][8]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][10]                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[14][1]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[13][8]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][1]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][11]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][0]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][10]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][8]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[0][9]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][9]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][8]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][7]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][6]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][5]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][4]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][3]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][2]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][1]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][0]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][11]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][10]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][5]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][9]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][8]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][7]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][6]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][4]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][4]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][10]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][3]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][2]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][1]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[5][0]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][11]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][10]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][9]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][8]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][7]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][6]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][5]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][4]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][3]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][2]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][1]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[4][0]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][11]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][0]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][1]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][2]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][3]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][4]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][5]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][6]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][7]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][8]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[3][9]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][3]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][2]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][1]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[12][0]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][11]                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][10]                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][9]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][8]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][7]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][6]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][5]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][3]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][2]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][1]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[11][0]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][11]                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][10]                                                                                                                                                                           ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][9]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][8]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][7]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][6]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][5]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][4]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][3]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][2]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][1]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[10][0]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][11]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][10]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][9]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][8]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][7]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][6]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][5]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][4]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][3]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][2]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][1]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[9][0]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][11]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][10]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][9]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][8]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][7]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][6]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][5]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][4]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][3]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][2]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][1]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[8][0]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][11]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][10]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][9]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][8]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][7]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][6]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][5]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][4]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][3]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][2]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][1]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[7][0]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][11]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[6][10]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][0]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][7]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][1]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][2]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][3]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][4]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][5]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][9]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][6]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][8]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][10]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][10]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][11]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][9]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[2][8]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_int_reg[1][11]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][1]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][2]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][3]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[16]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[14]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[15]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[12]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[13]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[10]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[11]                                                                                                                       ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[8]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[9]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[6]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[7]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[4]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[5]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[2]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[3]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[0]                                                                                                                        ; yes                                                              ; yes                                        ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15|dffe16a[1]                                                                                                                        ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe13a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe13a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe13a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe13a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe13a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe13a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe13a[1] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe17a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe17a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe17a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe17a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe17a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe17a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe17a[1] ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe18a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][11]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][10]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][9]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][8]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][7]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][6]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][5]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][4]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][3]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][2]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][1]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[4][0]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[6][4]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][11]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][10]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][9]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][8]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][7]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][6]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][5]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[3][4]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                             ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                              ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[10]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[11]                                           ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[8]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[9]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[6]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[7]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[4]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[5]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[2]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[3]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[0]                                            ; yes                                                              ; yes                                        ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16|dffe17a[1]                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][0]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][0]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][0]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][8]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][8]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][8]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][8]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][12]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][13]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][1]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][2]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][3]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][4]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][5]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][6]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][7]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][9]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][10]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][11]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][12]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[1][13]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][1]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][2]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][3]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][4]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][5]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][6]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][7]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][1]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][1]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][9]                                                                                                                                                                                ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][9]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][9]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][9]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][2]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][3]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][4]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][5]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][6]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][7]                                                                                                                                                                             ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][10]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[0][11]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][2]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][10]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][10]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][10]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][3]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][11]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][11]                                                                                                                                                                              ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][11]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][4]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][12]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][12]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][5]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][13]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_int_reg[2][13]                                                                                                                                                                            ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][6]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_reg[1][14]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_int_reg[9][7]                                                                                                                                                                               ; yes                                                              ; yes                                        ;
; Total number of protected registers is 1292                                                                                                                                                                                                                 ;                                                                  ;                                            ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                                     ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                                                                 ; Reason for Removal                                                                                                     ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_word_id[2]                                                                                                                                               ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[30]                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_counter[0,1]                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                 ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|init_done_forever                                                                                      ; Stuck at VCC due to stuck port data_in                                                                                 ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|count[0..6]                                                                                            ; Stuck at GND due to stuck port clock_enable                                                                            ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|rst_n[0,1]                                                                                             ; Lost fanout                                                                                                            ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|ser_shift_load                                                                                         ; Stuck at VCC due to stuck port data_in                                                                                 ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                           ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp|dffe12a[11]                                             ; Lost fanout                                                                                                            ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_6f9:ws_bwp|dffe14a[16]                                                                                                                       ; Lost fanout                                                                                                            ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_6f9:ws_brp|dffe14a[16]                                                                                                                       ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_bwp|dffe15a[6] ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_brp|dffe15a[6] ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_bwp|dffe12a[6]                                                                          ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_brp|dffe12a[6]                                                                          ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[26,27]                                                                                                                                       ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[25]                       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[9,11]                                                                                                                                                ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[10]                               ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_error[2]                                                                                                                                                      ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_cmd_process_error[3]                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_error[2]                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|ser_data_5_bits_filter:C_FILTER_SIN|sl_int_add[0]                                                ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[10]                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_error[7]                                                                                                                                                      ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[25]                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_error[7]                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                 ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET|sl_int_addr[1]                                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                 ;
; FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_int_state.ERR                                                                                                                                                  ; Lost fanout                                                                                                            ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~2                                                                                 ; Lost fanout                                                                                                            ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~3                                                                                 ; Lost fanout                                                                                                            ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~4                                                                                 ; Lost fanout                                                                                                            ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~5                                                                                 ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_DECODE_DELAY                                                                                                                                        ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_2FRM_PROCESS_DELAY               ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_NOT_ADRRESSED_DELAY                                                                                                                                 ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_2FRM_PROCESS_DELAY               ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_SET_CONFIG_CMD_PROCESS_DELAY                                                                                                                        ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_2FRM_PROCESS_DELAY               ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.WAIT_FIFO_PROCESS_DELAY                                                                                                                                 ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_2FRM_PROCESS_DELAY               ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state.GET_CONFIG_CMD_DELAY                                                                                                                               ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state.WR_DELAY                                                                                                                                           ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_2FRM_PROCESS_DELAY                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_RX_fifo_rd_cnt[0,1]                                                                                                                                           ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_wr_cnt[0,1]                                                                                                                                      ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_NOT_ADRRESSED                                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                 ;
; Total Number of Removed Registers = 84                                                                                                                                                                                        ;                                                                                                                        ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                                                       ;
+------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                            ; Reason for Removal             ; Registers Removed due to This Register                                                                                                ;
+------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|init_done_forever ; Stuck at VCC                   ; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|count[5],      ;
;                                                                                                                                          ; due to stuck port data_in      ; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|count[4],      ;
;                                                                                                                                          ;                                ; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|count[3],      ;
;                                                                                                                                          ;                                ; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|count[2]       ;
; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|count[6]          ; Stuck at GND                   ; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|rst_n[1],      ;
;                                                                                                                                          ; due to stuck port clock_enable ; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|rst_n[0],      ;
;                                                                                                                                          ;                                ; FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst|ser_shift_load ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_error[2]                                                                 ; Stuck at GND                   ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_error[2],                                                        ;
;                                                                                                                                          ; due to stuck port data_in      ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_RX_fifo_rd_cnt[1],                                                    ;
;                                                                                                                                          ;                                ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_RX_fifo_rd_cnt[0]                                                     ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_cmd_process_error[3]                                                     ; Stuck at GND                   ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_error[7],                                                             ;
;                                                                                                                                          ; due to stuck port data_in      ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_error[7]                                                         ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY                               ; Stuck at GND                   ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_wr_cnt[1],                                               ;
;                                                                                                                                          ; due to stuck port data_in      ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_wr_cnt[0]                                                ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_word_id[2]                                                          ; Stuck at GND                   ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[30]                                                  ;
;                                                                                                                                          ; due to stuck port data_in      ;                                                                                                                                       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[10]                                                             ; Stuck at GND                   ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[25]                                                  ;
;                                                                                                                                          ; due to stuck port data_in      ;                                                                                                                                       ;
+------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 5186  ;
; Number of registers using Synchronous Clear  ; 581   ;
; Number of registers using Synchronous Load   ; 436   ;
; Number of registers using Asynchronous Clear ; 4887  ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 1704  ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                                                                                                                         ; Fan out ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_wrn[1]                                                                                                                                                                     ; 1       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_pkendn                                                                                                                                                                     ; 1       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_startn[0]                                                                                                                                                                  ; 6       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_wrn[0]                                                                                                                                                                     ; 2       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_du6:rdptr_g1p|counter5a0    ; 9       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_startn[1]                                                                                                                                                                  ; 1       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_uc_full                                                                                                                                                                    ; 8       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_bg6:rdptr_g1p|counter5a0                                                                             ; 8       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|cntr_osd:cntr_b|counter_reg_bit0          ; 2       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_du6:rdptr_g1p|parity6       ; 6       ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_qdc:wrptr_g1p|counter8a0                                                                                                                           ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                               ; 10      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                               ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                               ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                               ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                 ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                 ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                 ; 10      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                 ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                 ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                 ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                               ; 10      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                               ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                               ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                               ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                 ; 11      ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|counter5a0                                                 ; 10      ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_7ub:wrptr_g1p|counter8a0                                                                             ; 8       ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_uv6:rdptr_g1p|counter5a0                                                                                                                           ; 9       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_bg6:rdptr_g1p|parity6                                                                                ; 5       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|cntr_osd:cntr_b|counter_reg_bit0          ; 2       ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_qdc:wrptr_g1p|parity9                                                                                                                              ; 5       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                  ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                  ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                  ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                  ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                    ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                    ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                    ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                    ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                    ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                    ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                  ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                  ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                  ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                  ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                    ; 7       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p|parity6                                                    ; 7       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_7ub:wrptr_g1p|parity9                                                                                ; 6       ;
; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_uv6:rdptr_g1p|parity6                                                                                                                              ; 6       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a0    ; 8       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_8cc:wrptr_g1p|sub_parity9a0 ; 1       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9       ; 6       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[0]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[8]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_cu6:rdptr_g1p|sub_parity6a0 ; 1       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                 ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                 ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                 ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                 ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                 ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                 ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                 ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                                 ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                               ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                               ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                               ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                               ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                               ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                               ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                               ; 6       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|counter8a0                                               ; 6       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[13]                                                                                                                                        ; 4       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[14]                                                                                                                                        ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[12]                                                                                                                                        ; 5       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[4]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[15]                                                                                                                                        ; 5       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[1]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[9]                                                                                                                                         ; 3       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                    ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                    ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                    ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                    ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                    ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                    ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                    ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                    ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                  ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                  ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                  ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                  ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                  ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                  ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                  ; 4       ;
; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p|parity9                                                  ; 4       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[10]                                                                                                                                        ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[11]                                                                                                                                        ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[6]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[7]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[2]                                                                                                                                         ; 3       ;
; Total number of inverted registers = 102*                                                                                                                                                                                                 ;         ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
* Table truncated at 100 items. To change the number of inverted registers reported, set the "Number of Inverted Registers Reported" option under Assignments->Settings->Analysis and Synthesis Settings->More Settings


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|sl_int_dpar_latch[5]                                                                                                                         ;
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_cmd_process_error[6]                                                         ;
; 3:1                ; 32 bits   ; 64 LEs        ; 0 LEs                ; 64 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_checksumH[30]                                                                            ;
; 3:1                ; 12 bits   ; 24 LEs        ; 0 LEs                ; 24 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_BCR_cnt[2]                                                                               ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_err_d[0]                                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|sl_int_err_d[3]                                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_counter[3]                                        ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER|sl_int_shift[5]     ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|sl_int_count[3] ;
; 3:1                ; 10 bits   ; 20 LEs        ; 0 LEs                ; 20 LEs                 ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|sl_int_shift[6] ;
; 3:1                ; 8 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|sl_int_err_cnt_pll_locked[4]                                                                                   ;
; 3:1                ; 14 bits   ; 28 LEs        ; 28 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET|sl_int_data[6]                                                                ;
; 4:1                ; 24 bits   ; 48 LEs        ; 0 LEs                ; 48 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_L1A_cnt[8]                                                                               ;
; 3:1                ; 31 bits   ; 62 LEs        ; 0 LEs                ; 62 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_data[157]                         ;
; 3:1                ; 20 bits   ; 40 LEs        ; 0 LEs                ; 40 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_data[23]                          ;
; 3:1                ; 112 bits  ; 224 LEs       ; 0 LEs                ; 224 LEs                ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_data[88]                          ;
; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_data[31]                          ;
; 3:1                ; 31 bits   ; 62 LEs        ; 0 LEs                ; 62 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_data[157]                         ;
; 3:1                ; 20 bits   ; 40 LEs        ; 0 LEs                ; 40 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_data[19]                          ;
; 3:1                ; 112 bits  ; 224 LEs       ; 0 LEs                ; 224 LEs                ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_data[109]                         ;
; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_data[35]                          ;
; 4:1                ; 13 bits   ; 26 LEs        ; 0 LEs                ; 26 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_cal_delay_cnt[6]                      ;
; 4:1                ; 13 bits   ; 26 LEs        ; 0 LEs                ; 26 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_cal_delay_cnt[1]                      ;
; 10:1               ; 12 bits   ; 72 LEs        ; 72 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET|sl_int_data[5]                                                                  ;
; 5:1                ; 20 bits   ; 60 LEs        ; 0 LEs                ; 60 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_cal_cnt[4]                            ;
; 5:1                ; 20 bits   ; 60 LEs        ; 0 LEs                ; 60 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_cal_cnt[13]                           ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX|sl_int_24b_cnt[2]             ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX|sl_int_24b_cnt[0]             ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX|sl_int_24b_cnt[0]             ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX|sl_int_24b_cnt[0]             ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX|sl_int_24b_cnt[2]             ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX|sl_int_24b_cnt[2]             ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX|sl_int_24b_cnt[2]             ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX|sl_int_24b_cnt[2]             ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED|sl_int_24b_cnt[2]               ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED|sl_int_24b_cnt[0]               ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED|sl_int_24b_cnt[0]               ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED|sl_int_24b_cnt[0]               ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED|sl_int_24b_cnt[2]               ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED|sl_int_24b_cnt[0]               ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED|sl_int_24b_cnt[2]               ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED|sl_int_24b_cnt[2]               ;
; 5:1                ; 6 bits    ; 18 LEs        ; 12 LEs               ; 6 LEs                  ; Yes        ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE|sl_int_phase_cnt[2]                                                             ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[4]                                                                  ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[5]                                                                  ;
; 5:1                ; 5 bits    ; 15 LEs        ; 10 LEs               ; 5 LEs                  ; Yes        ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET|sl_int_addr[4]                                                                  ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET|sl_int_addr[1]                                                                ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET|sl_int_addr[1]                                                                   ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_sc_counter[1]                                                                ;
; 8:1                ; 4 bits    ; 20 LEs        ; 16 LEs               ; 4 LEs                  ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_cmd_process_error[11]                                                        ;
; 7:1                ; 7 bits    ; 28 LEs        ; 7 LEs                ; 21 LEs                 ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_frame_cnt[3]                                                                 ;
; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_data[3]                           ;
; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_data[3]                           ;
; 8:1                ; 2 bits    ; 10 LEs        ; 6 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_data[6]                           ;
; 8:1                ; 2 bits    ; 10 LEs        ; 6 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_data[5]                           ;
; 20:1               ; 9 bits    ; 117 LEs       ; 108 LEs              ; 9 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_fifo_data[15]                                                                            ;
; 20:1               ; 3 bits    ; 39 LEs        ; 39 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_fifo_data[20]                                                                            ;
; 9:1                ; 2 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_data[1]                           ;
; 9:1                ; 2 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_data[2]                           ;
; 21:1               ; 2 bits    ; 28 LEs        ; 28 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_fifo_data[4]                                                                             ;
; 11:1               ; 3 bits    ; 21 LEs        ; 3 LEs                ; 18 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_frame_cnt[0]                                                                             ;
; 22:1               ; 6 bits    ; 84 LEs        ; 84 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_int_fifo_data[5]                                                                             ;
; 12:1               ; 2 bits    ; 16 LEs        ; 6 LEs                ; 10 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|sl_int_ser_nb[1]                             ;
; 12:1               ; 2 bits    ; 16 LEs        ; 6 LEs                ; 10 LEs                 ; Yes        ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|sl_int_ser_nb[1]                             ;
; 12:1               ; 5 bits    ; 40 LEs        ; 35 LEs               ; 5 LEs                  ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d16[8]                                                                  ;
; 13:1               ; 3 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d16[12]                                                                 ;
; 13:1               ; 2 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d16[6]                                                                  ;
; 13:1               ; 3 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d16[0]                                                                  ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[7]                                            ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_next_checksumL[22]                                                                           ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_next_L1_fifo_cnt                                                                             ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET|sl_next_state.STORE                                                           ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET|sl_next_state.ERR                                                             ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET|sl_next_state.ERR                                                               ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |FTR_TOP|FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET|sl_next_state.STORE                                                              ;
; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE|Mux0                                                                            ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX|x_fifo_din[8]                 ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX|x_fifo_din[6]                 ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX|x_fifo_din[25]                ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX|x_fifo_din[23]                ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX|x_fifo_din[22]                ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX|x_fifo_din[3]                 ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX|x_fifo_din[21]                ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX|x_fifo_din[12]                ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED|x_fifo_din[19]                  ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED|x_fifo_din[12]                  ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED|x_fifo_din[17]                  ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED|x_fifo_din[10]                  ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED|x_fifo_din[10]                  ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED|x_fifo_din[12]                  ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED|x_fifo_din[5]                   ;
; 4:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED|x_fifo_din[15]                  ;
; 8:1                ; 2 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Mux2                                                       ;
; 8:1                ; 2 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Mux1                                                       ;
; 16:1               ; 4 bits    ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|Mux2                                                                                            ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; No         ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|Selector16                                               ;
; 8:1                ; 33 bits   ; 165 LEs       ; 165 LEs              ; 0 LEs                  ; No         ; |FTR_TOP|FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|mux_2t7:mux13|l3_w29_n0_mux_dataout        ;
; 8:1                ; 4 bits    ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|Mux2                                                     ;
; 6:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_next_L1A_state.WAIT_PULSE                                                                    ;
; 7:1                ; 4 bits    ; 16 LEs        ; 12 LEs               ; 4 LEs                  ; No         ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|Selector3       ;
; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; No         ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|Selector10                                                                          ;
; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; No         ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|Selector11                                                                     ;
; 9:1                ; 16 bits   ; 96 LEs        ; 96 LEs               ; 0 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|x_L1_fifo_rd[1]                                                                                 ;
; 8:1                ; 3 bits    ; 15 LEs        ; 12 LEs               ; 3 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_next_timeout_state.NONE                                                                      ;
; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; No         ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER|Selector1           ;
; 9:1                ; 2 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Selector2                                                  ;
; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|Selector2                                                                            ;
; 10:1               ; 2 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; No         ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|Selector5                                                                                                      ;
; 10:1               ; 2 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|Selector3                                                                                                      ;
; 11:1               ; 2 bits    ; 14 LEs        ; 8 LEs                ; 6 LEs                  ; No         ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|Selector1                                                                                                      ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX|sl_next_state.TIMEOUT         ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX|sl_next_state.WAIT_END        ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX|sl_next_state.WAIT_PREAMBLE   ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX|sl_next_state.WAIT_END        ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX|sl_next_state.WAIT_PREAMBLE   ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX|sl_next_state.IDLE            ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX|sl_next_state.WAIT_PREAMBLE   ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX|sl_next_state.IDLE            ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX|sl_next_state.OVERFLOW        ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX|sl_next_state.WAIT_END        ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX|sl_next_state.WAIT_PREAMBLE   ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX|sl_next_state.IDLE            ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX|sl_next_state.RECEIVING       ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX|sl_next_state.WAIT_END        ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX|sl_next_state.WAIT_PREAMBLE   ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX|sl_next_state.IDLE            ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED|sl_next_state.RECEIVING         ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED|sl_next_state.WAIT_END          ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED|sl_next_state.TIMEOUT           ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED|sl_next_state.IDLE              ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED|sl_next_state.WAIT_PREAMBLE     ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED|sl_next_state.IDLE              ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED|sl_next_state.TIMEOUT           ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED|sl_next_state.IDLE              ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED|sl_next_state.RECEIVING         ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED|sl_next_state.WAIT_END          ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED|sl_next_state.TIMEOUT           ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED|sl_next_state.WAIT_END          ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED|sl_next_state.TIMEOUT           ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED|sl_next_state.IDLE              ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED|sl_next_state.OVERFLOW          ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED|sl_next_state.IDLE              ;
; 12:1               ; 6 bits    ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; No         ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|Selector6                                                                            ;
; 13:1               ; 6 bits    ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; No         ; |FTR_TOP|FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE|Selector9                                                                       ;
; 11:1               ; 3 bits    ; 21 LEs        ; 15 LEs               ; 6 LEs                  ; No         ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|Selector68                                                                          ;
; 11:1               ; 4 bits    ; 28 LEs        ; 16 LEs               ; 12 LEs                 ; No         ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|Selector69                                                                          ;
; 15:1               ; 3 bits    ; 30 LEs        ; 9 LEs                ; 21 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Selector20                                                 ;
; 15:1               ; 3 bits    ; 30 LEs        ; 9 LEs                ; 21 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Selector38                                                 ;
; 17:1               ; 2 bits    ; 22 LEs        ; 6 LEs                ; 16 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Selector15                                                 ;
; 17:1               ; 2 bits    ; 22 LEs        ; 6 LEs                ; 16 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Selector31                                                 ;
; 17:1               ; 2 bits    ; 22 LEs        ; 8 LEs                ; 14 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Selector18                                                 ;
; 17:1               ; 2 bits    ; 22 LEs        ; 8 LEs                ; 14 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM|Selector34                                                 ;
; 44:1               ; 10 bits   ; 290 LEs       ; 100 LEs              ; 190 LEs                ; No         ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|Selector14                                                                     ;
; 24:1               ; 3 bits    ; 48 LEs        ; 30 LEs               ; 18 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|Selector223                                  ;
; 24:1               ; 2 bits    ; 32 LEs        ; 20 LEs               ; 12 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|Selector230                                  ;
; 24:1               ; 2 bits    ; 32 LEs        ; 18 LEs               ; 14 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|Selector237                                  ;
; 24:1               ; 3 bits    ; 48 LEs        ; 30 LEs               ; 18 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|Selector224                                  ;
; 24:1               ; 2 bits    ; 32 LEs        ; 20 LEs               ; 12 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|Selector229                                  ;
; 24:1               ; 2 bits    ; 32 LEs        ; 18 LEs               ; 14 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|Selector227                                  ;
; 25:1               ; 3 bits    ; 48 LEs        ; 27 LEs               ; 21 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1|Selector234                                  ;
; 25:1               ; 3 bits    ; 48 LEs        ; 27 LEs               ; 21 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0|Selector233                                  ;
; 19:1               ; 6 bits    ; 72 LEs        ; 48 LEs               ; 24 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_next_state.STOP                                                                              ;
; 20:1               ; 7 bits    ; 91 LEs        ; 35 LEs               ; 56 LEs                 ; No         ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|Selector44                                                                          ;
; 21:1               ; 2 bits    ; 28 LEs        ; 14 LEs               ; 14 LEs                 ; No         ; |FTR_TOP|FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM|sl_next_state.TRB_TRAILER_WAIT                                                                  ;
; 50:1               ; 2 bits    ; 66 LEs        ; 22 LEs               ; 44 LEs                 ; No         ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|Selector35                                                                          ;
; 50:1               ; 2 bits    ; 66 LEs        ; 18 LEs               ; 48 LEs                 ; No         ; |FTR_TOP|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|Selector38                                                                          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------+
; Source assignments for Top-level Entity: |FTR_TOP                     ;
+------------------------------+-------+------+-------------------------+
; Assignment                   ; Value ; From ; To                      ;
+------------------------------+-------+------+-------------------------+
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_phase_pll_locked ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_phase_pll_locked ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_clk32            ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_clk32            ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_main_clk         ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_main_clk         ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_sel_clk          ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_sel_clk          ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_sct_tx_clk[1]    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_sct_tx_clk[1]    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_sct_tx_clk[0]    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_sct_tx_clk[0]    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_sct_rx_clk[1]    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_sct_rx_clk[1]    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_sct_rx_clk[0]    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_sct_rx_clk[0]    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_usb_ready        ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_usb_ready        ;
+------------------------------+-------+------+-------------------------+


+--------------------------------------------------------------+
; Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER         ;
+------------------------------+-------+------+----------------+
; Assignment                   ; Value ; From ; To             ;
+------------------------------+-------+------+----------------+
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_sel_clk ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_sel_clk ;
+------------------------------+-------+------+----------------+


+--------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i ;
+------------------------------+-------+------+----------------------------------------------------------------------+
; Assignment                   ; Value ; From ; To                                                                   ;
+------------------------------+-------+------+----------------------------------------------------------------------+
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; cntsel_temp[4]                                                       ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; cntsel_temp[4]                                                       ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; cntsel_temp[3]                                                       ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; cntsel_temp[3]                                                       ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; cntsel_temp[2]                                                       ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; cntsel_temp[2]                                                       ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; cntsel_temp[1]                                                       ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; cntsel_temp[1]                                                       ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; cntsel_temp[0]                                                       ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; cntsel_temp[0]                                                       ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gnd                                                                  ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gnd                                                                  ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_write                                                            ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_write                                                            ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[15]                                                    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[15]                                                    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[14]                                                    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[14]                                                    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[13]                                                    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[13]                                                    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[12]                                                    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[12]                                                    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[11]                                                    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[11]                                                    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[10]                                                    ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[10]                                                    ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[9]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[9]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[8]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[8]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[7]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[7]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[6]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[6]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[5]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[5]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[4]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[4]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[3]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[3]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[2]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[2]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[1]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[1]                                                     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; dps_writedata[0]                                                     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; dps_writedata[0]                                                     ;
+------------------------------+-------+------+----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                           ; Value ; From ; To                                                                                                        ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; PHYSICAL_SYNTHESIS_COMBO_LOGIC       ; OFF   ; -    ; -                                                                                                         ;
; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF   ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP  ; OFF   ; -    ; -                                                                                                         ;
; REMOVE_REDUNDANT_LOGIC_CELLS         ; OFF   ; -    ; -                                                                                                         ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                           ; Value ; From ; To                                                                                                        ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; PHYSICAL_SYNTHESIS_COMBO_LOGIC       ; OFF   ; -    ; -                                                                                                         ;
; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF   ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP  ; OFF   ; -    ; -                                                                                                         ;
; REMOVE_REDUNDANT_LOGIC_CELLS         ; OFF   ; -    ; -                                                                                                         ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                           ; Value ; From ; To                                                                                                        ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; PHYSICAL_SYNTHESIS_COMBO_LOGIC       ; OFF   ; -    ; -                                                                                                         ;
; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF   ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP  ; OFF   ; -    ; -                                                                                                         ;
; REMOVE_REDUNDANT_LOGIC_CELLS         ; OFF   ; -    ; -                                                                                                         ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                           ; Value ; From ; To                                                                                                        ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; PHYSICAL_SYNTHESIS_COMBO_LOGIC       ; OFF   ; -    ; -                                                                                                         ;
; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF   ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP  ; OFF   ; -    ; -                                                                                                         ;
; REMOVE_REDUNDANT_LOGIC_CELLS         ; OFF   ; -    ; -                                                                                                         ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                           ; Value ; From ; To                                                                                                        ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+
; PHYSICAL_SYNTHESIS_COMBO_LOGIC       ; OFF   ; -    ; -                                                                                                         ;
; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; OFF   ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP  ; OFF   ; -    ; -                                                                                                         ;
; REMOVE_REDUNDANT_LOGIC_CELLS         ; OFF   ; -    ; -                                                                                                         ;
+--------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-----------------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                                      ;
+-------------------------+-------------+------+-----------------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                                       ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                           ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                           ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                                     ;
+-------------------------+-------------+------+-----------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+---------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                                  ;
+-----------------------------+---------+------+---------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                                   ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                                   ;
+-----------------------------+---------+------+---------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                 ;
+---------------------------------+-------+------+-------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                     ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                      ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                      ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                      ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_bg6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                        ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                   ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_7ub:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                        ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                   ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|altsyncram_cia1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                       ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                        ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                              ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                               ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                              ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                               ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                         ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                          ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                          ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                          ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                          ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                          ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                              ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                               ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                              ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                               ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                         ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                          ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                          ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                          ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                          ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                          ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated ;
+---------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                                                              ;
+---------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                                                               ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                                                               ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                                                               ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                                                               ;
+---------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_cu6:rdptr_g1p ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                                                                 ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; sub_parity6a0                                                                                                                                                                                                      ;
; POWER_UP_LEVEL ; LOW   ; -    ; parity5                                                                                                                                                                                                            ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_9cc:wrptr_g1p ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                                                                 ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                                                                         ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                                                            ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|altsyncram_po91:fifo_ram ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                 ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                  ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                                                                   ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                                                                   ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                                                                   ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                                                                   ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                                                                   ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                     ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                      ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_brp ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_bwp ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                  ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                                                                   ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                                                                   ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                                                                   ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                                                                   ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                                                                   ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                     ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                      ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|cntr_osd:cntr_b ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                                                     ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter_reg_bit0                                                                                                                                                                                       ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated ;
+---------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                                                              ;
+---------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                                                               ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                                                               ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                                                               ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                                                               ;
+---------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_du6:rdptr_g1p ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                                                                 ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                                                                         ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                                                            ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_8cc:wrptr_g1p ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                                                                 ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; sub_parity9a0                                                                                                                                                                                                      ;
; POWER_UP_LEVEL ; LOW   ; -    ; parity8                                                                                                                                                                                                            ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|altsyncram_qo91:fifo_ram ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                 ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                  ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                                                                   ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                                                                   ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                                                                   ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                                                                   ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                                                                   ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                     ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                      ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                  ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                                                                   ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                                                                   ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                                                                   ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                                                                   ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                                                                   ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                     ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                      ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|cntr_osd:cntr_b ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                                                     ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter_reg_bit0                                                                                                                                                                                       ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+---------------------+
; Assignment                      ; Value ; From ; To                  ;
+---------------------------------+-------+------+---------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                   ;
+---------------------------------+-------+------+---------------------+


+-------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated ;
+---------------------------------------+-------+------+------------------------------------------+
; Assignment                            ; Value ; From ; To                                       ;
+---------------------------------------+-------+------+------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                        ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                        ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                        ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                        ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                  ;
+---------------------------------------+-------+------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_uv6:rdptr_g1p ;
+----------------+-------+------+---------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                          ;
+----------------+-------+------+---------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                  ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                     ;
+----------------+-------+------+---------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_qdc:wrptr_g1p ;
+----------------+-------+------+---------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                          ;
+----------------+-------+------+---------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                  ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                     ;
+----------------+-------+------+---------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram ;
+---------------------------------+--------------------+------+------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                         ;
+---------------------------------+--------------------+------+------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                          ;
+---------------------------------+--------------------+------+------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_6f9:rs_brp ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                 ;
+---------------------------------+-------+------+-------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_6f9:rs_bwp ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                 ;
+---------------------------------+-------+------+-------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp ;
+-----------------------------+------------------------+------+--------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                           ;
+-----------------------------+------------------------+------+--------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                            ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                            ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                            ;
+-----------------------------+------------------------+------+--------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15 ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_6f9:ws_brp ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                 ;
+---------------------------------+-------+------+-------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_6f9:ws_bwp ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                 ;
+---------------------------------+-------+------+-------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp ;
+-----------------------------+------------------------+------+--------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                           ;
+-----------------------------+------------------------+------+--------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                            ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                            ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                            ;
+-----------------------------+------------------------+------+--------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18 ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------+
; Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET ;
+-------------------+-------+------+-------------------------------------------------+
; Assignment        ; Value ; From ; To                                              ;
+-------------------+-------+------+-------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][14]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][13]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][12]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][11]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][10]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][9]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][8]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][7]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][6]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][5]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][4]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][3]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][2]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][1]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][0]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][14]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][13]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][12]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][11]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][10]                               ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][9]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][8]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][7]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][6]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][5]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][4]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][3]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][2]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][1]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][0]                                ;
+-------------------+-------+------+-------------------------------------------------+


+-------------------------------------------------------------------------------------+
; Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET ;
+-------------------+-------+------+--------------------------------------------------+
; Assignment        ; Value ; From ; To                                               ;
+-------------------+-------+------+--------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][0]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][11]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][10]                                ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][9]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][8]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][7]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][6]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][5]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][4]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][3]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][2]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][1]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][0]                                 ;
+-------------------+-------+------+--------------------------------------------------+


+---------------------------------------------------------------------------------------+
; Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET ;
+-------------------+-------+------+----------------------------------------------------+
; Assignment        ; Value ; From ; To                                                 ;
+-------------------+-------+------+----------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][13]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][12]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][13]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][12]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][13]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][12]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][0]                                   ;
+-------------------+-------+------+----------------------------------------------------+


+---------------------------------------------------------------------------------------+
; Source assignments for FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET ;
+-------------------+-------+------+----------------------------------------------------+
; Assignment        ; Value ; From ; To                                                 ;
+-------------------+-------+------+----------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][11]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][10]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][9]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][8]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][7]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][6]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][5]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][4]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][3]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][2]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][1]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[14][0]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][11]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][10]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][9]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][8]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][7]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][6]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][5]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][4]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][3]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][2]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][1]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[13][0]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][11]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][10]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][9]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][8]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][7]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][6]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][5]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][4]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][3]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][2]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][1]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[12][0]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][11]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][10]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][9]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][8]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][7]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][6]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][5]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][4]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][3]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][2]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][1]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[11][0]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][11]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][10]                                 ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][9]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][8]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][7]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][6]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][5]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][4]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][3]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][2]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][1]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[10][0]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[9][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[8][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[7][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[6][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[5][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[4][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[3][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[2][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[1][0]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][11]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][10]                                  ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][9]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][8]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][7]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][6]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][5]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][4]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][3]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][2]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][1]                                   ;
; PRESERVE_REGISTER ; on    ; -    ; sl_int_reg[0][0]                                   ;
+-------------------+-------+------+----------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                 ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                  ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                  ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                  ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                            ;
+---------------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                    ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                            ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                               ;
+----------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                          ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                           ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                     ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                      ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                         ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                   ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                    ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                    ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                    ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                                              ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                      ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                              ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                 ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                     ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                      ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                       ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                        ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                          ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                           ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                            ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                             ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                 ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                           ;
+-------------------------+-------------+------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                        ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                         ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                         ;
+-----------------------------+---------+------+-----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i ;
+--------------------------------------+------------------------+-------------------------------------------------------------------------------+
; Parameter Name                       ; Value                  ; Type                                                                          ;
+--------------------------------------+------------------------+-------------------------------------------------------------------------------+
; reference_clock_frequency            ; 40.0 MHz               ; String                                                                        ;
; fractional_vco_multiplier            ; false                  ; String                                                                        ;
; pll_type                             ; General                ; String                                                                        ;
; pll_subtype                          ; General                ; String                                                                        ;
; number_of_clocks                     ; 2                      ; Signed Integer                                                                ;
; operation_mode                       ; direct                 ; String                                                                        ;
; deserialization_factor               ; 4                      ; Signed Integer                                                                ;
; data_rate                            ; 0                      ; Signed Integer                                                                ;
; sim_additional_refclk_cycles_to_lock ; 0                      ; Signed Integer                                                                ;
; output_clock_frequency0              ; 40.000000 MHz          ; String                                                                        ;
; phase_shift0                         ; 0 ps                   ; String                                                                        ;
; duty_cycle0                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency1              ; 32.000000 MHz          ; String                                                                        ;
; phase_shift1                         ; 0 ps                   ; String                                                                        ;
; duty_cycle1                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency2              ; 0 MHz                  ; String                                                                        ;
; phase_shift2                         ; 0 ps                   ; String                                                                        ;
; duty_cycle2                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency3              ; 0 MHz                  ; String                                                                        ;
; phase_shift3                         ; 0 ps                   ; String                                                                        ;
; duty_cycle3                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency4              ; 0 MHz                  ; String                                                                        ;
; phase_shift4                         ; 0 ps                   ; String                                                                        ;
; duty_cycle4                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency5              ; 0 MHz                  ; String                                                                        ;
; phase_shift5                         ; 0 ps                   ; String                                                                        ;
; duty_cycle5                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency6              ; 0 MHz                  ; String                                                                        ;
; phase_shift6                         ; 0 ps                   ; String                                                                        ;
; duty_cycle6                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency7              ; 0 MHz                  ; String                                                                        ;
; phase_shift7                         ; 0 ps                   ; String                                                                        ;
; duty_cycle7                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency8              ; 0 MHz                  ; String                                                                        ;
; phase_shift8                         ; 0 ps                   ; String                                                                        ;
; duty_cycle8                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency9              ; 0 MHz                  ; String                                                                        ;
; phase_shift9                         ; 0 ps                   ; String                                                                        ;
; duty_cycle9                          ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency10             ; 0 MHz                  ; String                                                                        ;
; phase_shift10                        ; 0 ps                   ; String                                                                        ;
; duty_cycle10                         ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency11             ; 0 MHz                  ; String                                                                        ;
; phase_shift11                        ; 0 ps                   ; String                                                                        ;
; duty_cycle11                         ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency12             ; 0 MHz                  ; String                                                                        ;
; phase_shift12                        ; 0 ps                   ; String                                                                        ;
; duty_cycle12                         ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency13             ; 0 MHz                  ; String                                                                        ;
; phase_shift13                        ; 0 ps                   ; String                                                                        ;
; duty_cycle13                         ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency14             ; 0 MHz                  ; String                                                                        ;
; phase_shift14                        ; 0 ps                   ; String                                                                        ;
; duty_cycle14                         ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency15             ; 0 MHz                  ; String                                                                        ;
; phase_shift15                        ; 0 ps                   ; String                                                                        ;
; duty_cycle15                         ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency16             ; 0 MHz                  ; String                                                                        ;
; phase_shift16                        ; 0 ps                   ; String                                                                        ;
; duty_cycle16                         ; 50                     ; Signed Integer                                                                ;
; output_clock_frequency17             ; 0 MHz                  ; String                                                                        ;
; phase_shift17                        ; 0 ps                   ; String                                                                        ;
; duty_cycle17                         ; 50                     ; Signed Integer                                                                ;
; clock_name_0                         ;                        ; String                                                                        ;
; clock_name_1                         ;                        ; String                                                                        ;
; clock_name_2                         ;                        ; String                                                                        ;
; clock_name_3                         ;                        ; String                                                                        ;
; clock_name_4                         ;                        ; String                                                                        ;
; clock_name_5                         ;                        ; String                                                                        ;
; clock_name_6                         ;                        ; String                                                                        ;
; clock_name_7                         ;                        ; String                                                                        ;
; clock_name_8                         ;                        ; String                                                                        ;
; clock_name_global_0                  ; false                  ; String                                                                        ;
; clock_name_global_1                  ; false                  ; String                                                                        ;
; clock_name_global_2                  ; false                  ; String                                                                        ;
; clock_name_global_3                  ; false                  ; String                                                                        ;
; clock_name_global_4                  ; false                  ; String                                                                        ;
; clock_name_global_5                  ; false                  ; String                                                                        ;
; clock_name_global_6                  ; false                  ; String                                                                        ;
; clock_name_global_7                  ; false                  ; String                                                                        ;
; clock_name_global_8                  ; false                  ; String                                                                        ;
; m_cnt_hi_div                         ; 1                      ; Signed Integer                                                                ;
; m_cnt_lo_div                         ; 1                      ; Signed Integer                                                                ;
; m_cnt_bypass_en                      ; false                  ; String                                                                        ;
; m_cnt_odd_div_duty_en                ; false                  ; String                                                                        ;
; n_cnt_hi_div                         ; 1                      ; Signed Integer                                                                ;
; n_cnt_lo_div                         ; 1                      ; Signed Integer                                                                ;
; n_cnt_bypass_en                      ; false                  ; String                                                                        ;
; n_cnt_odd_div_duty_en                ; false                  ; String                                                                        ;
; c_cnt_hi_div0                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div0                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en0                     ; false                  ; String                                                                        ;
; c_cnt_in_src0                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en0               ; false                  ; String                                                                        ;
; c_cnt_prst0                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst0                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div1                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div1                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en1                     ; false                  ; String                                                                        ;
; c_cnt_in_src1                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en1               ; false                  ; String                                                                        ;
; c_cnt_prst1                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst1                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div2                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div2                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en2                     ; false                  ; String                                                                        ;
; c_cnt_in_src2                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en2               ; false                  ; String                                                                        ;
; c_cnt_prst2                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst2                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div3                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div3                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en3                     ; false                  ; String                                                                        ;
; c_cnt_in_src3                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en3               ; false                  ; String                                                                        ;
; c_cnt_prst3                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst3                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div4                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div4                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en4                     ; false                  ; String                                                                        ;
; c_cnt_in_src4                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en4               ; false                  ; String                                                                        ;
; c_cnt_prst4                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst4                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div5                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div5                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en5                     ; false                  ; String                                                                        ;
; c_cnt_in_src5                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en5               ; false                  ; String                                                                        ;
; c_cnt_prst5                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst5                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div6                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div6                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en6                     ; false                  ; String                                                                        ;
; c_cnt_in_src6                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en6               ; false                  ; String                                                                        ;
; c_cnt_prst6                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst6                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div7                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div7                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en7                     ; false                  ; String                                                                        ;
; c_cnt_in_src7                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en7               ; false                  ; String                                                                        ;
; c_cnt_prst7                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst7                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div8                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div8                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en8                     ; false                  ; String                                                                        ;
; c_cnt_in_src8                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en8               ; false                  ; String                                                                        ;
; c_cnt_prst8                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst8                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div9                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div9                        ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en9                     ; false                  ; String                                                                        ;
; c_cnt_in_src9                        ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en9               ; false                  ; String                                                                        ;
; c_cnt_prst9                          ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst9                   ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div10                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div10                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en10                    ; false                  ; String                                                                        ;
; c_cnt_in_src10                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en10              ; false                  ; String                                                                        ;
; c_cnt_prst10                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst10                  ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div11                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div11                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en11                    ; false                  ; String                                                                        ;
; c_cnt_in_src11                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en11              ; false                  ; String                                                                        ;
; c_cnt_prst11                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst11                  ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div12                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div12                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en12                    ; false                  ; String                                                                        ;
; c_cnt_in_src12                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en12              ; false                  ; String                                                                        ;
; c_cnt_prst12                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst12                  ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div13                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div13                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en13                    ; false                  ; String                                                                        ;
; c_cnt_in_src13                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en13              ; false                  ; String                                                                        ;
; c_cnt_prst13                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst13                  ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div14                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div14                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en14                    ; false                  ; String                                                                        ;
; c_cnt_in_src14                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en14              ; false                  ; String                                                                        ;
; c_cnt_prst14                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst14                  ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div15                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div15                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en15                    ; false                  ; String                                                                        ;
; c_cnt_in_src15                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en15              ; false                  ; String                                                                        ;
; c_cnt_prst15                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst15                  ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div16                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div16                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en16                    ; false                  ; String                                                                        ;
; c_cnt_in_src16                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en16              ; false                  ; String                                                                        ;
; c_cnt_prst16                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst16                  ; 0                      ; Signed Integer                                                                ;
; c_cnt_hi_div17                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_lo_div17                       ; 1                      ; Signed Integer                                                                ;
; c_cnt_bypass_en17                    ; false                  ; String                                                                        ;
; c_cnt_in_src17                       ; ph_mux_clk             ; String                                                                        ;
; c_cnt_odd_div_duty_en17              ; false                  ; String                                                                        ;
; c_cnt_prst17                         ; 1                      ; Signed Integer                                                                ;
; c_cnt_ph_mux_prst17                  ; 0                      ; Signed Integer                                                                ;
; pll_vco_div                          ; 1                      ; Signed Integer                                                                ;
; pll_slf_rst                          ; false                  ; String                                                                        ;
; pll_bw_sel                           ; low                    ; String                                                                        ;
; pll_output_clk_frequency             ; 0 MHz                  ; String                                                                        ;
; pll_cp_current                       ; 0                      ; Signed Integer                                                                ;
; pll_bwctrl                           ; 0                      ; Signed Integer                                                                ;
; pll_fractional_division              ; 1                      ; Signed Integer                                                                ;
; pll_fractional_cout                  ; 24                     ; Signed Integer                                                                ;
; pll_dsm_out_sel                      ; 1st_order              ; String                                                                        ;
; mimic_fbclk_type                     ; gclk                   ; String                                                                        ;
; pll_fbclk_mux_1                      ; glb                    ; String                                                                        ;
; pll_fbclk_mux_2                      ; fb_1                   ; String                                                                        ;
; pll_m_cnt_in_src                     ; ph_mux_clk             ; String                                                                        ;
; pll_vcoph_div                        ; 1                      ; Signed Integer                                                                ;
; refclk1_frequency                    ; 0 MHz                  ; String                                                                        ;
; pll_clkin_0_src                      ; clk_0                  ; String                                                                        ;
; pll_clkin_1_src                      ; clk_0                  ; String                                                                        ;
; pll_clk_loss_sw_en                   ; false                  ; String                                                                        ;
; pll_auto_clk_sw_en                   ; false                  ; String                                                                        ;
; pll_manu_clk_sw_en                   ; false                  ; String                                                                        ;
; pll_clk_sw_dly                       ; 0                      ; Signed Integer                                                                ;
; pll_extclk_0_cnt_src                 ; pll_extclk_cnt_src_vss ; String                                                                        ;
; pll_extclk_1_cnt_src                 ; pll_extclk_cnt_src_vss ; String                                                                        ;
+--------------------------------------+------------------------+-------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i ;
+--------------------------------------+------------------------+--------------------------------------------------------------------------+
; Parameter Name                       ; Value                  ; Type                                                                     ;
+--------------------------------------+------------------------+--------------------------------------------------------------------------+
; reference_clock_frequency            ; 40.0 MHz               ; String                                                                   ;
; fractional_vco_multiplier            ; false                  ; String                                                                   ;
; pll_type                             ; Cyclone V              ; String                                                                   ;
; pll_subtype                          ; DPS                    ; String                                                                   ;
; number_of_clocks                     ; 5                      ; Signed Integer                                                           ;
; operation_mode                       ; source synchronous     ; String                                                                   ;
; deserialization_factor               ; 4                      ; Signed Integer                                                           ;
; data_rate                            ; 0                      ; Signed Integer                                                           ;
; sim_additional_refclk_cycles_to_lock ; 0                      ; Signed Integer                                                           ;
; output_clock_frequency0              ; 40.000000 MHz          ; String                                                                   ;
; phase_shift0                         ; 0 ps                   ; String                                                                   ;
; duty_cycle0                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency1              ; 40.000000 MHz          ; String                                                                   ;
; phase_shift1                         ; 0 ps                   ; String                                                                   ;
; duty_cycle1                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency2              ; 40.000000 MHz          ; String                                                                   ;
; phase_shift2                         ; 0 ps                   ; String                                                                   ;
; duty_cycle2                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency3              ; 40.000000 MHz          ; String                                                                   ;
; phase_shift3                         ; 0 ps                   ; String                                                                   ;
; duty_cycle3                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency4              ; 40.000000 MHz          ; String                                                                   ;
; phase_shift4                         ; 0 ps                   ; String                                                                   ;
; duty_cycle4                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency5              ; 0 MHz                  ; String                                                                   ;
; phase_shift5                         ; 0 ps                   ; String                                                                   ;
; duty_cycle5                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency6              ; 0 MHz                  ; String                                                                   ;
; phase_shift6                         ; 0 ps                   ; String                                                                   ;
; duty_cycle6                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency7              ; 0 MHz                  ; String                                                                   ;
; phase_shift7                         ; 0 ps                   ; String                                                                   ;
; duty_cycle7                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency8              ; 0 MHz                  ; String                                                                   ;
; phase_shift8                         ; 0 ps                   ; String                                                                   ;
; duty_cycle8                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency9              ; 0 MHz                  ; String                                                                   ;
; phase_shift9                         ; 0 ps                   ; String                                                                   ;
; duty_cycle9                          ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency10             ; 0 MHz                  ; String                                                                   ;
; phase_shift10                        ; 0 ps                   ; String                                                                   ;
; duty_cycle10                         ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency11             ; 0 MHz                  ; String                                                                   ;
; phase_shift11                        ; 0 ps                   ; String                                                                   ;
; duty_cycle11                         ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency12             ; 0 MHz                  ; String                                                                   ;
; phase_shift12                        ; 0 ps                   ; String                                                                   ;
; duty_cycle12                         ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency13             ; 0 MHz                  ; String                                                                   ;
; phase_shift13                        ; 0 ps                   ; String                                                                   ;
; duty_cycle13                         ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency14             ; 0 MHz                  ; String                                                                   ;
; phase_shift14                        ; 0 ps                   ; String                                                                   ;
; duty_cycle14                         ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency15             ; 0 MHz                  ; String                                                                   ;
; phase_shift15                        ; 0 ps                   ; String                                                                   ;
; duty_cycle15                         ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency16             ; 0 MHz                  ; String                                                                   ;
; phase_shift16                        ; 0 ps                   ; String                                                                   ;
; duty_cycle16                         ; 50                     ; Signed Integer                                                           ;
; output_clock_frequency17             ; 0 MHz                  ; String                                                                   ;
; phase_shift17                        ; 0 ps                   ; String                                                                   ;
; duty_cycle17                         ; 50                     ; Signed Integer                                                           ;
; clock_name_0                         ;                        ; String                                                                   ;
; clock_name_1                         ;                        ; String                                                                   ;
; clock_name_2                         ;                        ; String                                                                   ;
; clock_name_3                         ;                        ; String                                                                   ;
; clock_name_4                         ;                        ; String                                                                   ;
; clock_name_5                         ;                        ; String                                                                   ;
; clock_name_6                         ;                        ; String                                                                   ;
; clock_name_7                         ;                        ; String                                                                   ;
; clock_name_8                         ;                        ; String                                                                   ;
; clock_name_global_0                  ; false                  ; String                                                                   ;
; clock_name_global_1                  ; false                  ; String                                                                   ;
; clock_name_global_2                  ; false                  ; String                                                                   ;
; clock_name_global_3                  ; false                  ; String                                                                   ;
; clock_name_global_4                  ; false                  ; String                                                                   ;
; clock_name_global_5                  ; false                  ; String                                                                   ;
; clock_name_global_6                  ; false                  ; String                                                                   ;
; clock_name_global_7                  ; false                  ; String                                                                   ;
; clock_name_global_8                  ; false                  ; String                                                                   ;
; m_cnt_hi_div                         ; 4                      ; Signed Integer                                                           ;
; m_cnt_lo_div                         ; 4                      ; Signed Integer                                                           ;
; m_cnt_bypass_en                      ; false                  ; String                                                                   ;
; m_cnt_odd_div_duty_en                ; false                  ; String                                                                   ;
; n_cnt_hi_div                         ; 256                    ; Signed Integer                                                           ;
; n_cnt_lo_div                         ; 256                    ; Signed Integer                                                           ;
; n_cnt_bypass_en                      ; true                   ; String                                                                   ;
; n_cnt_odd_div_duty_en                ; false                  ; String                                                                   ;
; c_cnt_hi_div0                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_lo_div0                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_bypass_en0                     ; false                  ; String                                                                   ;
; c_cnt_in_src0                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en0               ; false                  ; String                                                                   ;
; c_cnt_prst0                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst0                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div1                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_lo_div1                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_bypass_en1                     ; false                  ; String                                                                   ;
; c_cnt_in_src1                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en1               ; false                  ; String                                                                   ;
; c_cnt_prst1                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst1                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div2                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_lo_div2                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_bypass_en2                     ; false                  ; String                                                                   ;
; c_cnt_in_src2                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en2               ; false                  ; String                                                                   ;
; c_cnt_prst2                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst2                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div3                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_lo_div3                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_bypass_en3                     ; false                  ; String                                                                   ;
; c_cnt_in_src3                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en3               ; false                  ; String                                                                   ;
; c_cnt_prst3                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst3                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div4                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_lo_div4                        ; 4                      ; Signed Integer                                                           ;
; c_cnt_bypass_en4                     ; false                  ; String                                                                   ;
; c_cnt_in_src4                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en4               ; false                  ; String                                                                   ;
; c_cnt_prst4                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst4                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div5                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div5                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en5                     ; true                   ; String                                                                   ;
; c_cnt_in_src5                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en5               ; false                  ; String                                                                   ;
; c_cnt_prst5                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst5                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div6                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div6                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en6                     ; true                   ; String                                                                   ;
; c_cnt_in_src6                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en6               ; false                  ; String                                                                   ;
; c_cnt_prst6                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst6                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div7                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div7                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en7                     ; true                   ; String                                                                   ;
; c_cnt_in_src7                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en7               ; false                  ; String                                                                   ;
; c_cnt_prst7                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst7                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div8                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div8                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en8                     ; true                   ; String                                                                   ;
; c_cnt_in_src8                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en8               ; false                  ; String                                                                   ;
; c_cnt_prst8                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst8                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div9                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div9                        ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en9                     ; true                   ; String                                                                   ;
; c_cnt_in_src9                        ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en9               ; false                  ; String                                                                   ;
; c_cnt_prst9                          ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst9                   ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div10                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div10                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en10                    ; true                   ; String                                                                   ;
; c_cnt_in_src10                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en10              ; false                  ; String                                                                   ;
; c_cnt_prst10                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst10                  ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div11                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div11                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en11                    ; true                   ; String                                                                   ;
; c_cnt_in_src11                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en11              ; false                  ; String                                                                   ;
; c_cnt_prst11                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst11                  ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div12                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div12                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en12                    ; true                   ; String                                                                   ;
; c_cnt_in_src12                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en12              ; false                  ; String                                                                   ;
; c_cnt_prst12                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst12                  ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div13                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div13                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en13                    ; true                   ; String                                                                   ;
; c_cnt_in_src13                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en13              ; false                  ; String                                                                   ;
; c_cnt_prst13                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst13                  ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div14                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div14                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en14                    ; true                   ; String                                                                   ;
; c_cnt_in_src14                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en14              ; false                  ; String                                                                   ;
; c_cnt_prst14                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst14                  ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div15                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div15                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en15                    ; true                   ; String                                                                   ;
; c_cnt_in_src15                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en15              ; false                  ; String                                                                   ;
; c_cnt_prst15                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst15                  ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div16                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div16                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en16                    ; true                   ; String                                                                   ;
; c_cnt_in_src16                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en16              ; false                  ; String                                                                   ;
; c_cnt_prst16                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst16                  ; 0                      ; Signed Integer                                                           ;
; c_cnt_hi_div17                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_lo_div17                       ; 1                      ; Signed Integer                                                           ;
; c_cnt_bypass_en17                    ; true                   ; String                                                                   ;
; c_cnt_in_src17                       ; ph_mux_clk             ; String                                                                   ;
; c_cnt_odd_div_duty_en17              ; false                  ; String                                                                   ;
; c_cnt_prst17                         ; 1                      ; Signed Integer                                                           ;
; c_cnt_ph_mux_prst17                  ; 0                      ; Signed Integer                                                           ;
; pll_vco_div                          ; 2                      ; Signed Integer                                                           ;
; pll_slf_rst                          ; false                  ; String                                                                   ;
; pll_bw_sel                           ; low                    ; String                                                                   ;
; pll_output_clk_frequency             ; 320.0 MHz              ; String                                                                   ;
; pll_cp_current                       ; 20                     ; Signed Integer                                                           ;
; pll_bwctrl                           ; 4000                   ; Signed Integer                                                           ;
; pll_fractional_division              ; 1                      ; String                                                                   ;
; pll_fractional_cout                  ; 32                     ; Signed Integer                                                           ;
; pll_dsm_out_sel                      ; 1st_order              ; String                                                                   ;
; mimic_fbclk_type                     ; gclk                   ; String                                                                   ;
; pll_fbclk_mux_1                      ; glb                    ; String                                                                   ;
; pll_fbclk_mux_2                      ; fb_1                   ; String                                                                   ;
; pll_m_cnt_in_src                     ; ph_mux_clk             ; String                                                                   ;
; pll_vcoph_div                        ; 1                      ; Signed Integer                                                           ;
; refclk1_frequency                    ; 0 MHz                  ; String                                                                   ;
; pll_clkin_0_src                      ; clk_0                  ; String                                                                   ;
; pll_clkin_1_src                      ; clk_0                  ; String                                                                   ;
; pll_clk_loss_sw_en                   ; false                  ; String                                                                   ;
; pll_auto_clk_sw_en                   ; false                  ; String                                                                   ;
; pll_manu_clk_sw_en                   ; false                  ; String                                                                   ;
; pll_clk_sw_dly                       ; 0                      ; Signed Integer                                                           ;
; pll_extclk_0_cnt_src                 ; pll_extclk_cnt_src_vss ; String                                                                   ;
; pll_extclk_1_cnt_src                 ; pll_extclk_cnt_src_vss ; String                                                                   ;
+--------------------------------------+------------------------+--------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE ;
+----------------+-------+----------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                             ;
+----------------+-------+----------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                       ;
+----------------+-------+----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB ;
+-----------------------------+-------+-------------------------------------------+
; Parameter Name              ; Value ; Type                                      ;
+-----------------------------+-------+-------------------------------------------+
; x_reset_active              ; '0'   ; Enumerated                                ;
; x_nb_config_word16          ; 1     ; Signed Integer                            ;
; x_nb_config_word16_size     ; 1     ; Signed Integer                            ;
; x_nb_dpram_size             ; 1     ; Signed Integer                            ;
; x_nb_devices_size           ; 0     ; Signed Integer                            ;
; x_uc_data_size              ; 32    ; Signed Integer                            ;
; x_uc_dma_size_w32           ; 11    ; Signed Integer                            ;
; x_uc_dma_nb_w32             ; 2048  ; Signed Integer                            ;
; x_chain_en                  ; '0'   ; Enumerated                                ;
; x_fifo_tx_size              ; 6     ; Signed Integer                            ;
; x_fifo_tx_thd_stop_flow     ; 32    ; Signed Integer                            ;
; x_fifo_tx_thd_restart_flow  ; 16    ; Signed Integer                            ;
; x_timeout_prescaler_ms_size ; 16    ; Signed Integer                            ;
; x_timeout_prescaler_ms_nb   ; 39998 ; Signed Integer                            ;
; x_timeout_ms_size           ; 10    ; Signed Integer                            ;
; x_timeout_ms                ; 500   ; Signed Integer                            ;
+-----------------------------+-------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB ;
+-------------------+-------+--------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                     ;
+-------------------+-------+--------------------------------------------------------------------------+
; x_uc_data_size    ; 32    ; Signed Integer                                                           ;
; x_uc_dma_size_w32 ; 11    ; Signed Integer                                                           ;
; x_uc_dma_nb_w32   ; 2048  ; Signed Integer                                                           ;
; x_fifo_tx_size    ; 6     ; Signed Integer                                                           ;
; x_reset_active    ; '0'   ; Enumerated                                                               ;
+-------------------+-------+--------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+----------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                                 ;
+------------------------+--------------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                           ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                                         ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                                         ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                                       ;
; WIDTH                  ; 1            ; Signed Integer                                                                                                       ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                              ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                              ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                              ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                              ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                              ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                              ;
+------------------------+--------------+----------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                             ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                          ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                       ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                     ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                     ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                   ;
; LPM_WIDTH               ; 33          ; Signed Integer                                                                                   ;
; LPM_NUMWORDS            ; 64          ; Signed Integer                                                                                   ;
; LPM_WIDTHU              ; 6           ; Signed Integer                                                                                   ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                          ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                          ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                          ;
; USE_EAB                 ; ON          ; Untyped                                                                                          ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                          ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                          ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                          ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                          ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                   ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                   ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                          ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                          ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                          ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                          ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                          ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                          ;
; CBXI_PARAMETER          ; dcfifo_85n1 ; Untyped                                                                                          ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                      ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                ;
+----------------+-------+-------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC ;
+-----------------+-------+--------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                   ;
+-----------------+-------+--------------------------------------------------------------------------------------------------------+
; x_reset_active  ; '0'   ; Enumerated                                                                                             ;
; x_din_byte_nb   ; 2     ; Signed Integer                                                                                         ;
; x_crc_din_width ; 4     ; Signed Integer                                                                                         ;
; x_crc_width     ; 16    ; Signed Integer                                                                                         ;
+-----------------+-------+--------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER ;
+-------------------------+-------+--------------------------------------------------------------------------+
; Parameter Name          ; Value ; Type                                                                     ;
+-------------------------+-------+--------------------------------------------------------------------------+
; x_reset_active          ; '0'   ; Enumerated                                                               ;
; x_nb_config_word16      ; 1     ; Signed Integer                                                           ;
; x_nb_config_word16_size ; 1     ; Signed Integer                                                           ;
; x_nb_dpram_size         ; 1     ; Signed Integer                                                           ;
; x_nb_devices_size       ; 0     ; Signed Integer                                                           ;
; x_fifo_tx_size          ; 6     ; Signed Integer                                                           ;
; x_fifo_tx_wr_duration   ; 00    ; Unsigned Binary                                                          ;
; x_enable_timeout        ; '1'   ; Enumerated                                                               ;
; x_timeout_ms_size       ; 10    ; Signed Integer                                                           ;
; x_timeout_ms            ; 500   ; Signed Integer                                                           ;
+-------------------------+-------+--------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER ;
+-----------------------------+-------+-----------------------------------------------------------------+
; Parameter Name              ; Value ; Type                                                            ;
+-----------------------------+-------+-----------------------------------------------------------------+
; x_reset_active              ; '0'   ; Enumerated                                                      ;
; x_nb_config_word16          ; 1     ; Signed Integer                                                  ;
; x_nb_dpram_size             ; 1     ; Signed Integer                                                  ;
; x_nb_devices_size           ; 0     ; Signed Integer                                                  ;
; x_chain_en                  ; '0'   ; Enumerated                                                      ;
; x_fifo_rx_rd_duration       ; 00    ; Unsigned Binary                                                 ;
; x_enable_timeout            ; '1'   ; Enumerated                                                      ;
; x_timeout_prescaler_ms_size ; 16    ; Signed Integer                                                  ;
; x_timeout_prescaler_ms_nb   ; 39998 ; Signed Integer                                                  ;
; x_timeout_ms_size           ; 10    ; Signed Integer                                                  ;
; x_timeout_ms                ; 500   ; Signed Integer                                                  ;
+-----------------------------+-------+-----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART ;
+------------------+-------------------+------------------------------------------------------------------+
; Parameter Name   ; Value             ; Type                                                             ;
+------------------+-------------------+------------------------------------------------------------------+
; x_reset_active   ; '0'               ; Enumerated                                                       ;
; x_no_prescaler   ; '0'               ; Enumerated                                                       ;
; x_prescaler_size ; 4                 ; Signed Integer                                                   ;
; x_fifo_width     ; 32                ; Signed Integer                                                   ;
; x_fifotx_depth   ; 6                 ; Signed Integer                                                   ;
; x_fiforx_depth   ; 6                 ; Signed Integer                                                   ;
; x_impl_type      ; WRAPPER_32RX_32TX ; String                                                           ;
+------------------+-------------------+------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1 ;
+------------------+-------+---------------------------------------------------------------------------------------------------------+
; Parameter Name   ; Value ; Type                                                                                                    ;
+------------------+-------+---------------------------------------------------------------------------------------------------------+
; x_reset_active   ; '0'   ; Enumerated                                                                                              ;
; x_no_prescaler   ; '0'   ; Enumerated                                                                                              ;
; x_prescaler_size ; 4     ; Signed Integer                                                                                          ;
; x_fifo_width     ; 32    ; Signed Integer                                                                                          ;
; x_fifotx_depth   ; 6     ; Signed Integer                                                                                          ;
+------------------+-------+---------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART ;
+------------------+-------+-------------------------------------------------------------------------------------------------------------------------+
; Parameter Name   ; Value ; Type                                                                                                                    ;
+------------------+-------+-------------------------------------------------------------------------------------------------------------------------+
; x_reset_active   ; '0'   ; Enumerated                                                                                                              ;
; x_no_prescaler   ; '0'   ; Enumerated                                                                                                              ;
; x_prescaler_size ; 4     ; Signed Integer                                                                                                          ;
+------------------+-------+-------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_bdgen:\g_dbgen:C_BDGEN ;
+------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name   ; Value ; Type                                                                                                                                                    ;
+------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active   ; '0'   ; Enumerated                                                                                                                                              ;
; x_prescaler_size ; 4     ; Signed Integer                                                                                                                                          ;
+------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                             ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                                                                       ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component ;
+-------------------------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                            ; Value       ; Type                                                                                                                                                    ;
+-------------------------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; ACF_DISABLE_EMBEDDED_TIMING_CONSTRAINT    ; FALSE       ; Untyped                                                                                                                                                 ;
; ACF_DISABLE_MLAB_RAM_USE                  ; FALSE       ; Untyped                                                                                                                                                 ;
; ADD_RAM_OUTPUT_REGISTER                   ; OFF         ; Untyped                                                                                                                                                 ;
; ADD_USEDW_MSB_BIT                         ; OFF         ; Untyped                                                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED                   ; FALSE       ; Untyped                                                                                                                                                 ;
; DELAY_RDUSEDW                             ; 1           ; Untyped                                                                                                                                                 ;
; DELAY_WRUSEDW                             ; 1           ; Untyped                                                                                                                                                 ;
; DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT ; FALSE       ; Untyped                                                                                                                                                 ;
; ENABLE_ECC                                ; FALSE       ; Untyped                                                                                                                                                 ;
; LPM_NUMWORDS                              ; 64          ; Signed Integer                                                                                                                                          ;
; LPM_SHOWAHEAD                             ; OFF         ; Untyped                                                                                                                                                 ;
; LPM_WIDTH                                 ; 32          ; Signed Integer                                                                                                                                          ;
; LPM_WIDTH_R                               ; 8           ; Signed Integer                                                                                                                                          ;
; LPM_WIDTHU                                ; 6           ; Signed Integer                                                                                                                                          ;
; LPM_WIDTHU_R                              ; 8           ; Signed Integer                                                                                                                                          ;
; MAXIMIZE_SPEED                            ; 5           ; Untyped                                                                                                                                                 ;
; OVERFLOW_CHECKING                         ; ON          ; Untyped                                                                                                                                                 ;
; RAM_BLOCK_TYPE                            ; AUTO        ; Untyped                                                                                                                                                 ;
; RDSYNC_DELAYPIPE                          ; 4           ; Signed Integer                                                                                                                                          ;
; READ_ACLR_SYNCH                           ; OFF         ; Untyped                                                                                                                                                 ;
; UNDERFLOW_CHECKING                        ; ON          ; Untyped                                                                                                                                                 ;
; USE_EAB                                   ; ON          ; Untyped                                                                                                                                                 ;
; WRITE_ACLR_SYNCH                          ; OFF         ; Untyped                                                                                                                                                 ;
; WRSYNC_DELAYPIPE                          ; 4           ; Signed Integer                                                                                                                                          ;
; CBXI_PARAMETER                            ; dcfifo_8tq1 ; Untyped                                                                                                                                                 ;
+-------------------------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component ;
+-------------------------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                            ; Value       ; Type                                                                                                                                                    ;
+-------------------------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; ACF_DISABLE_EMBEDDED_TIMING_CONSTRAINT    ; FALSE       ; Untyped                                                                                                                                                 ;
; ACF_DISABLE_MLAB_RAM_USE                  ; FALSE       ; Untyped                                                                                                                                                 ;
; ADD_RAM_OUTPUT_REGISTER                   ; OFF         ; Untyped                                                                                                                                                 ;
; ADD_USEDW_MSB_BIT                         ; OFF         ; Untyped                                                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED                   ; FALSE       ; Untyped                                                                                                                                                 ;
; DELAY_RDUSEDW                             ; 1           ; Untyped                                                                                                                                                 ;
; DELAY_WRUSEDW                             ; 1           ; Untyped                                                                                                                                                 ;
; DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT ; FALSE       ; Untyped                                                                                                                                                 ;
; ENABLE_ECC                                ; FALSE       ; Untyped                                                                                                                                                 ;
; LPM_NUMWORDS                              ; 256         ; Signed Integer                                                                                                                                          ;
; LPM_SHOWAHEAD                             ; OFF         ; Untyped                                                                                                                                                 ;
; LPM_WIDTH                                 ; 8           ; Signed Integer                                                                                                                                          ;
; LPM_WIDTH_R                               ; 32          ; Signed Integer                                                                                                                                          ;
; LPM_WIDTHU                                ; 8           ; Signed Integer                                                                                                                                          ;
; LPM_WIDTHU_R                              ; 6           ; Signed Integer                                                                                                                                          ;
; MAXIMIZE_SPEED                            ; 5           ; Untyped                                                                                                                                                 ;
; OVERFLOW_CHECKING                         ; ON          ; Untyped                                                                                                                                                 ;
; RAM_BLOCK_TYPE                            ; AUTO        ; Untyped                                                                                                                                                 ;
; RDSYNC_DELAYPIPE                          ; 4           ; Signed Integer                                                                                                                                          ;
; READ_ACLR_SYNCH                           ; OFF         ; Untyped                                                                                                                                                 ;
; UNDERFLOW_CHECKING                        ; ON          ; Untyped                                                                                                                                                 ;
; USE_EAB                                   ; ON          ; Untyped                                                                                                                                                 ;
; WRITE_ACLR_SYNCH                          ; OFF         ; Untyped                                                                                                                                                 ;
; WRSYNC_DELAYPIPE                          ; 4           ; Signed Integer                                                                                                                                          ;
; CBXI_PARAMETER                            ; dcfifo_a5q1 ; Untyped                                                                                                                                                 ;
+-------------------------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component ;
+-------------------------+-------------+----------------------------------------------------+
; Parameter Name          ; Value       ; Type                                               ;
+-------------------------+-------------+----------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                            ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                         ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                       ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                       ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                     ;
; LPM_WIDTH               ; 33          ; Signed Integer                                     ;
; LPM_NUMWORDS            ; 65536       ; Signed Integer                                     ;
; LPM_WIDTHU              ; 16          ; Signed Integer                                     ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                            ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                            ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                            ;
; USE_EAB                 ; ON          ; Untyped                                            ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                            ;
; ENABLE_ECC              ; FALSE       ; Untyped                                            ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                            ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                            ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                     ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                     ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                            ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                            ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                            ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                            ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                            ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                            ;
; CBXI_PARAMETER          ; dcfifo_kvr1 ; Untyped                                            ;
+-------------------------+-------------+----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type                                       ;
+----------------+-------+--------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                 ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET ;
+---------------------+-------+----------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                       ;
+---------------------+-------+----------------------------------------------------------------------------+
; x_reset_active      ; '0'   ; Enumerated                                                                 ;
; x_nb_addr_bits      ; 1     ; Signed Integer                                                             ;
; x_nb_data_word      ; 2     ; Signed Integer                                                             ;
; x_user_set_cmd_size ; 16    ; Signed Integer                                                             ;
+---------------------+-------+----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET ;
+---------------------+-------+----------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                       ;
+---------------------+-------+----------------------------------------------------------------------------+
; x_reset_active      ; '0'   ; Enumerated                                                                 ;
; x_nb_addr_bits      ; 1     ; Signed Integer                                                             ;
; x_nb_data_word      ; 2     ; Signed Integer                                                             ;
; x_user_get_cmd_size ; 4     ; Signed Integer                                                             ;
+---------------------+-------+----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET ;
+---------------------+-------+-----------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                        ;
+---------------------+-------+-----------------------------------------------------------------------------+
; x_reset_active      ; '0'   ; Enumerated                                                                  ;
; x_nb_addr_bits      ; 4     ; Signed Integer                                                              ;
; x_nb_data_word      ; 10    ; Signed Integer                                                              ;
; x_user_set_cmd_size ; 16    ; Signed Integer                                                              ;
+---------------------+-------+-----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET ;
+---------------------+-------+-----------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                        ;
+---------------------+-------+-----------------------------------------------------------------------------+
; x_reset_active      ; '0'   ; Enumerated                                                                  ;
; x_nb_addr_bits      ; 4     ; Signed Integer                                                              ;
; x_nb_data_word      ; 10    ; Signed Integer                                                              ;
; x_user_get_cmd_size ; 4     ; Signed Integer                                                              ;
+---------------------+-------+-----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET ;
+---------------------+-------+-------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                          ;
+---------------------+-------+-------------------------------------------------------------------------------+
; x_reset_active      ; '0'   ; Enumerated                                                                    ;
; x_nb_addr_bits      ; 2     ; Signed Integer                                                                ;
; x_nb_data_word      ; 3     ; Signed Integer                                                                ;
; x_user_set_cmd_size ; 16    ; Signed Integer                                                                ;
+---------------------+-------+-------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET ;
+---------------------+-------+-------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                          ;
+---------------------+-------+-------------------------------------------------------------------------------+
; x_reset_active      ; '0'   ; Enumerated                                                                    ;
; x_nb_addr_bits      ; 2     ; Signed Integer                                                                ;
; x_nb_data_word      ; 3     ; Signed Integer                                                                ;
; x_user_get_cmd_size ; 4     ; Signed Integer                                                                ;
+---------------------+-------+-------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET ;
+---------------------+-------+-------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                          ;
+---------------------+-------+-------------------------------------------------------------------------------+
; x_reset_active      ; '0'   ; Enumerated                                                                    ;
; x_nb_addr_bits      ; 4     ; Signed Integer                                                                ;
; x_nb_data_word      ; 15    ; Signed Integer                                                                ;
; x_user_set_cmd_size ; 16    ; Signed Integer                                                                ;
+---------------------+-------+-------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_REG_WRAPPER:C_REGS|UFP_USER_SETGET_ACK:C_GET_ACK ;
+----------------+-------+--------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                     ;
+----------------+-------+--------------------------------------------------------------------------+
; x_user_nb      ; 3     ; Signed Integer                                                           ;
+----------------+-------+--------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER ;
+----------------------+-------+------------------------------------------+
; Parameter Name       ; Value ; Type                                     ;
+----------------------+-------+------------------------------------------+
; x_reset_active       ; '0'   ; Enumerated                               ;
; x_l2_fifo_depth_size ; 16    ; Signed Integer                           ;
; x_l2_fifo_not_full   ; 53248 ; Signed Integer                           ;
; x_l1_fifo_depth_size ; 11    ; Signed Integer                           ;
; x_nbmodules          ; 8     ; Signed Integer                           ;
+----------------------+-------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM ;
+----------------------+-------+------------------------------------------------------------+
; Parameter Name       ; Value ; Type                                                       ;
+----------------------+-------+------------------------------------------------------------+
; x_reset_active       ; '0'   ; Enumerated                                                 ;
; x_l2_fifo_depth_size ; 16    ; Signed Integer                                             ;
; x_l2_fifo_not_full   ; 53248 ; Signed Integer                                             ;
; x_nbmodules          ; 8     ; Signed Integer                                             ;
+----------------------+-------+------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM ;
+-------------------+-------+----------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                       ;
+-------------------+-------+----------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                 ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                             ;
; x_nbmodules       ; 8     ; Signed Integer                                                             ;
+-------------------+-------+----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:1:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:2:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:3:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:4:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:5:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:6:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:7:C_RXDMM_LED ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                          ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                    ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                ;
+-------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:0:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:1:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:2:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:3:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:4:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:5:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:6:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LEDX:7:C_RXDMM_LEDX ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                                                                            ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active    ; '0'   ; Enumerated                                                                                                                      ;
; x_fifo_depth_size ; 11    ; Signed Integer                                                                                                                  ;
+-------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                         ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                      ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                   ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                 ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                               ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                               ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                               ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                               ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                      ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                      ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                      ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                      ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                      ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                      ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                      ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                      ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                               ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                      ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                      ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                      ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                      ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                      ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                      ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                      ;
+-------------------------+-------------+------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                                           ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                                                        ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                                 ;
; LPM_WIDTH               ; 26          ; Signed Integer                                                                                                                 ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                                                                                 ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                        ;
; USE_EAB                 ; ON          ; Untyped                                                                                                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                                                        ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                                        ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                                        ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                                                        ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                                                        ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                                                        ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                        ;
; CBXI_PARAMETER          ; dcfifo_jtr1 ; Untyped                                                                                                                        ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC ;
+----------------+-------+-------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                    ;
+----------------+-------+-------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                              ;
+----------------+-------+-------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                  ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                            ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0 ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                                          ;
; x_module_nb    ; 4     ; Signed Integer                                                                                                      ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller1 ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                                          ;
; x_module_nb    ; 4     ; Signed Integer                                                                                                      ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:0:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:1:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:2:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP0:3:C_CMD0_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:0:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:1:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:2:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP0:3:C_CMD1_PP0|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:4:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:5:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:6:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD0_PP1:7:C_CMD0_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:4:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:5:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:6:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CMD1_PP1:7:C_CMD1_PP1|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                       ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                               ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                             ;
; WIDTH                  ; 1            ; Signed Integer                                                                                             ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                    ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                    ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                    ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                    ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                    ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                    ;
+------------------------+--------------+------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; dcfifo Parameter Settings by Entity Instance                                                                                                           ;
+----------------------------+---------------------------------------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                                                     ;
+----------------------------+---------------------------------------------------------------------------------------------------------------------------+
; Number of entity instances ; 18                                                                                                                        ;
; Entity Instance            ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component                               ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 33                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 64                                                                                                                        ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component                                                                             ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 33                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 65536                                                                                                                     ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component   ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED|dcfifo:dcfifo_component   ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED|dcfifo:dcfifo_component   ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED|dcfifo:dcfifo_component   ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED|dcfifo:dcfifo_component   ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED|dcfifo:dcfifo_component   ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED|dcfifo:dcfifo_component   ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED|dcfifo:dcfifo_component   ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
; Entity Instance            ; FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                                                                                                ;
;     -- LPM_WIDTH           ; 26                                                                                                                        ;
;     -- LPM_NUMWORDS        ; 2048                                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                                       ;
;     -- USE_EAB             ; ON                                                                                                                        ;
+----------------------------+---------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:7:C_CLK1_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:6:C_CLK1_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:5:C_CLK1_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP1:4:C_CLK1_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:7:C_CLK0_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:6:C_CLK0_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:5:C_CLK0_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP1:4:C_CLK0_PP1" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:3:C_CLK1_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:2:C_CLK1_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:1:C_CLK1_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK1_PP0:0:C_CLK1_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:3:C_CLK0_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:2:C_CLK0_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:1:C_CLK0_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|USB_UC_PCLK:\C_GEN_CLK0_PP0:0:C_CLK0_PP0" ;
+----------+-------+----------+-------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                           ;
+----------+-------+----------+-------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                      ;
+----------+-------+----------+-------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:7:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:6:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:5:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:4:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:3:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:2:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:1:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDXS:0:C_FIFO_LEDX"          ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:7:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:6:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:5:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:4:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:3:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:2:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:1:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED"            ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                  ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+
; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_FaserWrapper:C_WRAPPER"                                                                             ;
+--------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                     ; Type   ; Severity ; Details                                                                             ;
+--------------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_sct_cmd1_0_g           ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_detect_state0_g        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_rx_detect_reset_g      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_l2sm_err_timeout_l1a_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_pcsm_state0_g          ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_pcsm_ack01_g           ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_pcsm_state_ack_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_pcsm_busy0_g           ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------------------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET"                                   ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                             ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_sel_user_set_cmd ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_user_set_cmd     ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_busy             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET" ;
+--------------------------+-------+----------+----------------------------------------------+
; Port                     ; Type  ; Severity ; Details                                      ;
+--------------------------+-------+----------+----------------------------------------------+
; x_sel_user_get_cmd[3..1] ; Input ; Info     ; Stuck at GND                                 ;
; x_sel_user_get_cmd[0]    ; Input ; Info     ; Stuck at VCC                                 ;
+--------------------------+-------+----------+----------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET"                                   ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                             ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_sel_user_set_cmd ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_user_set_cmd     ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_busy             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET" ;
+--------------------------+-------+----------+--------------------------------------------+
; Port                     ; Type  ; Severity ; Details                                    ;
+--------------------------+-------+----------+--------------------------------------------+
; x_sel_user_get_cmd[3..2] ; Input ; Info     ; Stuck at GND                               ;
; x_sel_user_get_cmd[1]    ; Input ; Info     ; Stuck at VCC                               ;
; x_sel_user_get_cmd[0]    ; Input ; Info     ; Stuck at GND                               ;
+--------------------------+-------+----------+--------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET"                                     ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                             ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_sel_user_set_cmd ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_user_set_cmd     ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_busy             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET" ;
+--------------------+-------+----------+-------------------------------------------------+
; Port               ; Type  ; Severity ; Details                                         ;
+--------------------+-------+----------+-------------------------------------------------+
; x_sel_user_get_cmd ; Input ; Info     ; Stuck at GND                                    ;
+--------------------+-------+----------+-------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET"                                      ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                             ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_sel_user_set_cmd ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_user_set_cmd     ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_busy             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_REG_WRAPPER:C_REGS"                                                                                ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                    ; Type   ; Severity ; Details                                                                             ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_phase_regs[29..24]    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_config_regs[119..109] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_soft_cnt_regs[41..36] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_L2_FIFO:C_L2_FIFO"                                                                 ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                             ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; rdusedw ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER" ;
+------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+
; Port             ; Type   ; Severity ; Details                                                                                                           ;
+------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+
; x_rd             ; Input  ; Info     ; Stuck at VCC                                                                                                      ;
; x_overrun_err    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_state_g        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_shift_g        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_count_g        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_clk_count_g    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_start_detect_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_parity_calc_g  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_parity_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_clkpulse_g     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
+------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER" ;
+-------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+
; Port        ; Type   ; Severity ; Details                                                                                                            ;
+-------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+
; x_ready     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                ;
; x_state_g   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                ;
; x_parity_g  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                ;
; x_shift_g   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                ;
; x_tx_done_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                ;
+-------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_bdgen:\g_dbgen:C_BDGEN" ;
+---------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+
; Port          ; Type   ; Severity ; Details                                                                                                                       ;
+---------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+
; x_counter16_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                           ;
; x_counter_g   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                           ;
+---------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART"                                      ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                             ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_baudrate16      ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_parity_en       ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_parity_odd      ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_fiforx_rd_usedw ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_error           ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_error_clr       ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_flush           ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_pulse_out_g     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_pulse16_out_g   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER"                                         ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                    ; Type   ; Severity ; Details                                                                             ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_lib_fw_version[15..4] ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_lib_fw_version[2..0]  ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_lib_fw_version[3]     ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_fifo_tx_wr_lsb        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC" ;
+-----------------------+-------+----------+----------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                              ;
+-----------------------+-------+----------+----------------------------------------------------------------------+
; x_crc_init            ; Input ; Info     ; Stuck at VCC                                                         ;
; x_crc_final           ; Input ; Info     ; Stuck at GND                                                         ;
; x_crc_din_msb_1st     ; Input ; Info     ; Stuck at GND                                                         ;
; x_crc_reflect_crc_din ; Input ; Info     ; Stuck at VCC                                                         ;
; x_crc_reflect_crc     ; Input ; Info     ; Stuck at GND                                                         ;
+-----------------------+-------+----------+----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK" ;
+----------+-------+----------+-----------------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                                     ;
+----------+-------+----------+-----------------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                                ;
; datain_l ; Input ; Info     ; Stuck at VCC                                                                ;
+----------+-------+----------+-----------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB"                                  ;
+------------+--------+----------+-------------------------------------------------------------------------------------+
; Port       ; Type   ; Severity ; Details                                                                             ;
+------------+--------+----------+-------------------------------------------------------------------------------------+
; x_zlp_rq_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB"                                                                    ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                    ; Type   ; Severity ; Details                                                                             ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_uart_tx_en            ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_usb_stop_flow         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_sc_config             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_board_id_ans_dis      ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_board_id[6..4]        ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_status[15..7]         ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_fw_version[4..1]      ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_fw_version[15..5]     ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_fw_version[0]         ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_hw_version            ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_product_id[15..3]     ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_product_id[2]         ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_product_id[1]         ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_product_id[0]         ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_dpram_data_rd         ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_dpram_addr_rd         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_dpram_data_wr         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_dpram_addr_wr         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_dpram_wr              ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_device_load_req       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_device_load_ack       ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_device_load_error     ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_device_valid_word     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_user_set_req[7..6]    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_user_set_ack[7..6]    ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_user_set_error[7..6]  ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_user_set_cmd_req      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_user_set_cmd          ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_user_set_cmd_ack      ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_user_set_cmd_error    ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_user_set_cmd_error_d  ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_user_get_cmd[15..4]   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_state_g               ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_wr_cnt_g              ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_data_av_g             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fiforx_wr_req_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fiforx_wr_full_g      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fiforx_rd_req_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fiforx_rd_dout_g      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fiforx_rd_empty_g     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fifotx_rd_req_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fifotx_rd_empty_g     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fifotx_wr_req_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fifotx_wr_full_g      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fifotx_wr_din_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fiforeadout_tx_wr_g   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fiforeadout_tx_full_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_crc_dout_av_g         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_crc_dout_g            ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_answer_rq_g           ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "FTR_CLK_WRAPPER:C_CLK_WRAPPER"                                                                  ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port             ; Type   ; Severity ; Details                                                                             ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_phase_state_g  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_switch_state_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_pll4_locked_g  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------------+-----------------------+
; Type                        ; Count                 ;
+-----------------------------+-----------------------+
; arriav_ddio_out             ; 33                    ;
; arriav_ff                   ; 5186                  ;
;     CLR                     ; 2836                  ;
;     CLR SCLR                ; 382                   ;
;     CLR SCLR SLD            ; 12                    ;
;     CLR SLD                 ; 2                     ;
;     ENA                     ; 49                    ;
;     ENA CLR                 ; 1074                  ;
;     ENA CLR SCLR            ; 159                   ;
;     ENA CLR SCLR SLD        ; 24                    ;
;     ENA CLR SLD             ; 398                   ;
;     SCLR                    ; 4                     ;
;     plain                   ; 246                   ;
; arriav_io_obuf              ; 49                    ;
; arriav_lcell_comb           ; 5386                  ;
;     arith                   ; 498                   ;
;         0 data inputs       ; 2                     ;
;         1 data inputs       ; 430                   ;
;         2 data inputs       ; 34                    ;
;         5 data inputs       ; 32                    ;
;     extend                  ; 23                    ;
;         7 data inputs       ; 23                    ;
;     normal                  ; 4661                  ;
;         0 data inputs       ; 22                    ;
;         1 data inputs       ; 80                    ;
;         2 data inputs       ; 653                   ;
;         3 data inputs       ; 441                   ;
;         4 data inputs       ; 704                   ;
;         5 data inputs       ; 650                   ;
;         6 data inputs       ; 2111                  ;
;     shared                  ; 204                   ;
;         2 data inputs       ; 204                   ;
; boundary_port               ; 203                   ;
; cyclonev_fractional_pll     ; 1                     ;
; cyclonev_pll_output_counter ; 5                     ;
; cyclonev_pll_reconfig       ; 1                     ;
; cyclonev_pll_refclk_select  ; 1                     ;
; generic_pll                 ; 2                     ;
; stratixv_ram_block          ; 729                   ;
;                             ;                       ;
; Max LUT depth               ; 10.00                 ;
; Average LUT depth           ; 3.45                  ;
+-----------------------------+-----------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:16     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition
    Info: Processing started: Thu Nov 26 13:16:07 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FTR_TOP -c FTR_TOP
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/u_util/exp/u_size.vhd
    Info (12022): Found design unit 1: U_Size File: J:/vhdl_db/trunk/lib/u_util/exp/u_size.vhd Line: 10
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/u_util/exp/u_util.vhd
    Info (12022): Found design unit 1: u_util File: J:/vhdl_db/trunk/lib/u_util/exp/u_util.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/u_util/src/u_onepulse.vhd
    Info (12022): Found design unit 1: U_OnePulse-A_behavioral File: J:/vhdl_db/trunk/lib/u_util/src/u_onepulse.vhd Line: 26
    Info (12023): Found entity 1: U_OnePulse File: J:/vhdl_db/trunk/lib/u_util/src/u_onepulse.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/usb_l2_tx_fifo.vhd
    Info (12022): Found design unit 1: usb_l2_tx_fifo-SYN File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd Line: 59
    Info (12023): Found entity 1: USB_L2_TX_FIFO File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd Line: 42
Info (12021): Found 2 design units, including 0 entities, in source file /vhdl_db/trunk/lib/usb_usb/exp/usb_usb.vhd
    Info (12022): Found design unit 1: usb_usb File: J:/vhdl_db/trunk/lib/usb_usb/exp/USB_USB.vhd Line: 11
    Info (12022): Found design unit 2: usb_usb-body File: J:/vhdl_db/trunk/lib/usb_usb/exp/USB_USB.vhd Line: 245
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/usb_uc_pclk.vhd
    Info (12022): Found design unit 1: usb_uc_pclk-SYN File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 53
    Info (12023): Found entity 1: USB_UC_PCLK File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/usb_usb/src/usb_usb_reader.vhd
    Info (12022): Found design unit 1: USB_USB_Reader-Behavioral File: J:/vhdl_db/trunk/lib/usb_usb/src/USB_USB_Reader.vhd Line: 49
    Info (12023): Found entity 1: USB_USB_Reader File: J:/vhdl_db/trunk/lib/usb_usb/src/USB_USB_Reader.vhd Line: 11
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/exp/ser_serialcommunication.vhd
    Info (12022): Found design unit 1: ser_serialCommunication File: J:/vhdl_db/trunk/lib/ser_serialCommunication/exp/ser_serialCommunication.vhd Line: 14
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/exp/ser_crc_pck.vhd
    Info (12022): Found design unit 1: ser_crc_pck File: J:/vhdl_db/trunk/lib/ser_serialCommunication/exp/ser_crc_pck.vhd Line: 9
Info (12021): Found 2 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_crc_pck_polynomial.vhd
    Info (12022): Found design unit 1: ser_crc_pck_polynomial File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc_pck_polynomial.vhd Line: 13
    Info (12022): Found design unit 2: ser_crc_pck_polynomial-body File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc_pck_polynomial.vhd Line: 78
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_crc.vhd
    Info (12022): Found design unit 1: ser_crc-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc.vhd Line: 44
    Info (12023): Found entity 1: ser_crc File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc.vhd Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/crc_pol/ser_crc_pol16_din16_d4_1a2eb.vhd
    Info (12022): Found design unit 1: ser_crc_pol16_DIN16_D4_1a2eb-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd Line: 32
    Info (12023): Found entity 1: ser_crc_pol16_DIN16_D4_1a2eb File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_uart_ser.vhd
    Info (12022): Found design unit 1: ser_uart_ser-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_ser.vhd Line: 45
    Info (12023): Found entity 1: ser_uart_ser File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_ser.vhd Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_uart_deser.vhd
    Info (12022): Found design unit 1: ser_uart_deser-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_deser.vhd Line: 50
    Info (12023): Found entity 1: ser_uart_deser File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_deser.vhd Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_data_5_bits_filter.vhd
    Info (12022): Found design unit 1: ser_data_5_bits_filter-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_data_5_bits_filter.vhd Line: 21
    Info (12023): Found entity 1: ser_data_5_bits_filter File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_data_5_bits_filter.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_uart_bdgen.vhd
    Info (12022): Found design unit 1: ser_uart_bdgen-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_bdgen.vhd Line: 38
    Info (12023): Found entity 1: ser_uart_bdgen File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_bdgen.vhd Line: 10
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_uart.vhd
    Info (12022): Found design unit 1: ser_uart-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart.vhd Line: 61
    Info (12023): Found entity 1: ser_uart File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart.vhd Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_uart_wrapper.vhd
    Info (12022): Found design unit 1: ser_uart_wrapper-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper.vhd Line: 74
    Info (12023): Found entity 1: ser_uart_wrapper File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper.vhd Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_uart_wrapper32.vhd
    Info (12022): Found design unit 1: ser_uart_wrapper32-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper32.vhd Line: 71
    Info (12023): Found entity 1: ser_uart_wrapper32 File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper32.vhd Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/c_cyclone5/src/ser_uart_fifo_tx32.vhd
    Info (12022): Found design unit 1: ser_uart_fifo_tx32-SYN File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd Line: 59
    Info (12023): Found entity 1: SER_UART_FIFO_TX32 File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/c_cyclone5/src/ser_uart_fifo_rx32.vhd
    Info (12022): Found design unit 1: ser_uart_fifo_rx32-SYN File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd Line: 58
    Info (12023): Found entity 1: SER_UART_FIFO_RX32 File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd Line: 42
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/exp/ufp_usbfrontendprotocol.vhd
    Info (12022): Found design unit 1: UFP_UsbFrontEndProtocol File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_UsbFrontEndProtocol.vhd Line: 16
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/exp/ufp_protocol.vhd
    Info (12022): Found design unit 1: UFP_Protocol File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_Protocol.vhd Line: 14
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/exp/ufp_fw_version.vhd
    Info (12022): Found design unit 1: UFP_fw_version File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_fw_version.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_decoder.vhd
    Info (12022): Found design unit 1: UFP_DECODER-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Decoder.vhd Line: 75
    Info (12023): Found entity 1: UFP_DECODER File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Decoder.vhd Line: 9
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_encoder_uart.vhd
    Info (12022): Found design unit 1: UFP_ENCODER_UART-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Encoder_uart.vhd Line: 68
    Info (12023): Found entity 1: UFP_ENCODER_UART File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Encoder_uart.vhd Line: 10
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_wrapper_usb_uart.vhd
    Info (12022): Found design unit 1: UFP_WRAPPER_USB_UART-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 132
    Info (12023): Found entity 1: UFP_WRAPPER_USB_UART File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_user_get_config.vhd
    Info (12022): Found design unit 1: UFP_USER_GET_CONFIG-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_GET_CONFIG.vhd Line: 39
    Info (12023): Found entity 1: UFP_USER_GET_CONFIG File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_GET_CONFIG.vhd Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_user_set_config.vhd
    Info (12022): Found design unit 1: UFP_USER_SET_CONFIG-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SET_CONFIG.vhd Line: 43
    Info (12023): Found entity 1: UFP_USER_SET_CONFIG File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SET_CONFIG.vhd Line: 17
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_user_setget_ack.vhd
    Info (12022): Found design unit 1: UFP_USER_SETGET_ACK-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SETGET_ACK.vhd Line: 22
    Info (12023): Found entity 1: UFP_USER_SETGET_ACK File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SETGET_ACK.vhd Line: 10
Info (12021): Found 2 design units, including 1 entities, in source file src/pll_main.vhd
    Info (12022): Found design unit 1: PLL_MAIN-rtl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN.vhd Line: 21
    Info (12023): Found entity 1: PLL_MAIN File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN.vhd Line: 11
Info (12021): Found 1 design units, including 1 entities, in source file src/pll_main/pll_main_0002.v
    Info (12023): Found entity 1: PLL_MAIN_0002 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN/PLL_MAIN_0002.v Line: 2
Info (12021): Found 2 design units, including 1 entities, in source file src/pll_4k.vhd
    Info (12022): Found design unit 1: PLL_4K-rtl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K.vhd Line: 29
    Info (12023): Found entity 1: PLL_4K File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K.vhd Line: 11
Info (12021): Found 1 design units, including 1 entities, in source file src/pll_4k/pll_4k_0002.v
    Info (12023): Found entity 1: PLL_4K_0002 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K/PLL_4K_0002.v Line: 2
Info (12021): Found 2 design units, including 1 entities, in source file src/ftr_fine_phase_sm.vhd
    Info (12022): Found design unit 1: FTR_FINE_PHASE_SM-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FINE_PHASE_SM.vhd Line: 37
    Info (12023): Found entity 1: FTR_FINE_PHASE_SM File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FINE_PHASE_SM.vhd Line: 10
Info (12021): Found 2 design units, including 1 entities, in source file src/ftr_patchpanelcontrollersm.vhd
    Info (12022): Found design unit 1: FTR_PatchPanelControllerSM-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PatchPanelControllerSM.vhd Line: 51
    Info (12023): Found entity 1: FTR_PatchPanelControllerSM File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PatchPanelControllerSM.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file src/ftr_planecontrollersm.vhd
    Info (12022): Found design unit 1: FTR_PlaneControllerSM-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneControllerSM.vhd Line: 69
    Info (12023): Found entity 1: FTR_PlaneControllerSM File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneControllerSM.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file src/ftr_planecontroller.vhd
    Info (12022): Found design unit 1: FTR_PlaneController-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneController.vhd Line: 70
    Info (12023): Found entity 1: FTR_PlaneController File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneController.vhd Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file src/ftr_rxdatamodulemanager.vhd
    Info (12022): Found design unit 1: FTR_RXDataModuleManager-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataModuleManager.vhd Line: 40
    Info (12023): Found entity 1: FTR_RXDataModuleManager File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataModuleManager.vhd Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file src/ftr_rxdataplanemanager.vhd
    Info (12022): Found design unit 1: FTR_RXDataPlaneManager-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataPlaneManager.vhd Line: 48
    Info (12023): Found entity 1: FTR_RXDataPlaneManager File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataPlaneManager.vhd Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file src/ftr_l2_sm.vhd
    Info (12022): Found design unit 1: FTR_L2_SM-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_SM.vhd Line: 61
    Info (12023): Found entity 1: FTR_L2_SM File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_SM.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file src/ftr_faserwrapper.vhd
    Info (12022): Found design unit 1: FTR_FaserWrapper-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FaserWrapper.vhd Line: 150
    Info (12023): Found entity 1: FTR_FaserWrapper File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FaserWrapper.vhd Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file src/ftr_clk_wrapper.vhd
    Info (12022): Found design unit 1: FTR_CLK_WRAPPER-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_CLK_WRAPPER.vhd Line: 52
    Info (12023): Found entity 1: FTR_CLK_WRAPPER File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_CLK_WRAPPER.vhd Line: 17
Info (12021): Found 2 design units, including 1 entities, in source file src/ftr_reg_wrapper.vhd
    Info (12022): Found design unit 1: FTR_REG_WRAPPER-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 54
    Info (12023): Found entity 1: FTR_REG_WRAPPER File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 18
Info (12021): Found 2 design units, including 1 entities, in source file src/ftr_l2_fifo.vhd
    Info (12022): Found design unit 1: ftr_l2_fifo-SYN File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_FIFO.vhd Line: 60
    Info (12023): Found entity 1: FTR_L2_FIFO File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_FIFO.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file src/ftr_l1_fifo.vhd
    Info (12022): Found design unit 1: ftr_l1_fifo-SYN File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L1_FIFO.vhd Line: 60
    Info (12023): Found entity 1: FTR_L1_FIFO File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L1_FIFO.vhd Line: 42
Info (12021): Found 1 design units, including 0 entities, in source file src/ftr_global_const.vhd
    Info (12022): Found design unit 1: FTR_GLOBAL_CONST File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_GLOBAL_CONST.vhd Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file src/ftr_top.vhd
    Info (12022): Found design unit 1: FTR_TOP-Behavioral File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 209
    Info (12023): Found entity 1: FTR_TOP File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 16
Info (12127): Elaborating entity "FTR_TOP" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at FTR_TOP.vhd(333): object "sl_int_sct_cmd1_0_g" assigned a value but never read File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 333
Warning (10036): Verilog HDL or VHDL warning at FTR_TOP.vhd(339): object "sl_int_l2sm_err_TIMEOUT_L1A_g" assigned a value but never read File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 339
Info (12128): Elaborating entity "FTR_CLK_WRAPPER" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 356
Info (12128): Elaborating entity "PLL_MAIN" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_CLK_WRAPPER.vhd Line: 104
Info (12128): Elaborating entity "PLL_MAIN_0002" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN.vhd Line: 34
Info (12128): Elaborating entity "altera_pll" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN/PLL_MAIN_0002.v Line: 88
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus
Info (12130): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN/PLL_MAIN_0002.v Line: 88
Info (12133): Instantiated megafunction "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i" with the following parameter: File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_MAIN/PLL_MAIN_0002.v Line: 88
    Info (12134): Parameter "fractional_vco_multiplier" = "false"
    Info (12134): Parameter "reference_clock_frequency" = "40.0 MHz"
    Info (12134): Parameter "operation_mode" = "direct"
    Info (12134): Parameter "number_of_clocks" = "2"
    Info (12134): Parameter "output_clock_frequency0" = "40.000000 MHz"
    Info (12134): Parameter "phase_shift0" = "0 ps"
    Info (12134): Parameter "duty_cycle0" = "50"
    Info (12134): Parameter "output_clock_frequency1" = "32.000000 MHz"
    Info (12134): Parameter "phase_shift1" = "0 ps"
    Info (12134): Parameter "duty_cycle1" = "50"
    Info (12134): Parameter "output_clock_frequency2" = "0 MHz"
    Info (12134): Parameter "phase_shift2" = "0 ps"
    Info (12134): Parameter "duty_cycle2" = "50"
    Info (12134): Parameter "output_clock_frequency3" = "0 MHz"
    Info (12134): Parameter "phase_shift3" = "0 ps"
    Info (12134): Parameter "duty_cycle3" = "50"
    Info (12134): Parameter "output_clock_frequency4" = "0 MHz"
    Info (12134): Parameter "phase_shift4" = "0 ps"
    Info (12134): Parameter "duty_cycle4" = "50"
    Info (12134): Parameter "output_clock_frequency5" = "0 MHz"
    Info (12134): Parameter "phase_shift5" = "0 ps"
    Info (12134): Parameter "duty_cycle5" = "50"
    Info (12134): Parameter "output_clock_frequency6" = "0 MHz"
    Info (12134): Parameter "phase_shift6" = "0 ps"
    Info (12134): Parameter "duty_cycle6" = "50"
    Info (12134): Parameter "output_clock_frequency7" = "0 MHz"
    Info (12134): Parameter "phase_shift7" = "0 ps"
    Info (12134): Parameter "duty_cycle7" = "50"
    Info (12134): Parameter "output_clock_frequency8" = "0 MHz"
    Info (12134): Parameter "phase_shift8" = "0 ps"
    Info (12134): Parameter "duty_cycle8" = "50"
    Info (12134): Parameter "output_clock_frequency9" = "0 MHz"
    Info (12134): Parameter "phase_shift9" = "0 ps"
    Info (12134): Parameter "duty_cycle9" = "50"
    Info (12134): Parameter "output_clock_frequency10" = "0 MHz"
    Info (12134): Parameter "phase_shift10" = "0 ps"
    Info (12134): Parameter "duty_cycle10" = "50"
    Info (12134): Parameter "output_clock_frequency11" = "0 MHz"
    Info (12134): Parameter "phase_shift11" = "0 ps"
    Info (12134): Parameter "duty_cycle11" = "50"
    Info (12134): Parameter "output_clock_frequency12" = "0 MHz"
    Info (12134): Parameter "phase_shift12" = "0 ps"
    Info (12134): Parameter "duty_cycle12" = "50"
    Info (12134): Parameter "output_clock_frequency13" = "0 MHz"
    Info (12134): Parameter "phase_shift13" = "0 ps"
    Info (12134): Parameter "duty_cycle13" = "50"
    Info (12134): Parameter "output_clock_frequency14" = "0 MHz"
    Info (12134): Parameter "phase_shift14" = "0 ps"
    Info (12134): Parameter "duty_cycle14" = "50"
    Info (12134): Parameter "output_clock_frequency15" = "0 MHz"
    Info (12134): Parameter "phase_shift15" = "0 ps"
    Info (12134): Parameter "duty_cycle15" = "50"
    Info (12134): Parameter "output_clock_frequency16" = "0 MHz"
    Info (12134): Parameter "phase_shift16" = "0 ps"
    Info (12134): Parameter "duty_cycle16" = "50"
    Info (12134): Parameter "output_clock_frequency17" = "0 MHz"
    Info (12134): Parameter "phase_shift17" = "0 ps"
    Info (12134): Parameter "duty_cycle17" = "50"
    Info (12134): Parameter "pll_type" = "General"
    Info (12134): Parameter "pll_subtype" = "General"
Info (12128): Elaborating entity "PLL_4K" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_CLK_WRAPPER.vhd Line: 116
Info (12128): Elaborating entity "PLL_4K_0002" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K.vhd Line: 50
Info (12128): Elaborating entity "altera_pll" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K/PLL_4K_0002.v Line: 263
Warning (10034): Output port "lvds_clk" at altera_pll.v(319) has no driver File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 319
Warning (10034): Output port "loaden" at altera_pll.v(320) has no driver File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 320
Warning (10034): Output port "extclk_out" at altera_pll.v(321) has no driver File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 321
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus
Info (12130): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K/PLL_4K_0002.v Line: 263
Info (12133): Instantiated megafunction "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" with the following parameter: File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/PLL_4K/PLL_4K_0002.v Line: 263
    Info (12134): Parameter "fractional_vco_multiplier" = "false"
    Info (12134): Parameter "reference_clock_frequency" = "40.0 MHz"
    Info (12134): Parameter "pll_fractional_cout" = "32"
    Info (12134): Parameter "pll_dsm_out_sel" = "1st_order"
    Info (12134): Parameter "operation_mode" = "source synchronous"
    Info (12134): Parameter "number_of_clocks" = "5"
    Info (12134): Parameter "output_clock_frequency0" = "40.000000 MHz"
    Info (12134): Parameter "phase_shift0" = "0 ps"
    Info (12134): Parameter "duty_cycle0" = "50"
    Info (12134): Parameter "output_clock_frequency1" = "40.000000 MHz"
    Info (12134): Parameter "phase_shift1" = "0 ps"
    Info (12134): Parameter "duty_cycle1" = "50"
    Info (12134): Parameter "output_clock_frequency2" = "40.000000 MHz"
    Info (12134): Parameter "phase_shift2" = "0 ps"
    Info (12134): Parameter "duty_cycle2" = "50"
    Info (12134): Parameter "output_clock_frequency3" = "40.000000 MHz"
    Info (12134): Parameter "phase_shift3" = "0 ps"
    Info (12134): Parameter "duty_cycle3" = "50"
    Info (12134): Parameter "output_clock_frequency4" = "40.000000 MHz"
    Info (12134): Parameter "phase_shift4" = "0 ps"
    Info (12134): Parameter "duty_cycle4" = "50"
    Info (12134): Parameter "output_clock_frequency5" = "0 MHz"
    Info (12134): Parameter "phase_shift5" = "0 ps"
    Info (12134): Parameter "duty_cycle5" = "50"
    Info (12134): Parameter "output_clock_frequency6" = "0 MHz"
    Info (12134): Parameter "phase_shift6" = "0 ps"
    Info (12134): Parameter "duty_cycle6" = "50"
    Info (12134): Parameter "output_clock_frequency7" = "0 MHz"
    Info (12134): Parameter "phase_shift7" = "0 ps"
    Info (12134): Parameter "duty_cycle7" = "50"
    Info (12134): Parameter "output_clock_frequency8" = "0 MHz"
    Info (12134): Parameter "phase_shift8" = "0 ps"
    Info (12134): Parameter "duty_cycle8" = "50"
    Info (12134): Parameter "output_clock_frequency9" = "0 MHz"
    Info (12134): Parameter "phase_shift9" = "0 ps"
    Info (12134): Parameter "duty_cycle9" = "50"
    Info (12134): Parameter "output_clock_frequency10" = "0 MHz"
    Info (12134): Parameter "phase_shift10" = "0 ps"
    Info (12134): Parameter "duty_cycle10" = "50"
    Info (12134): Parameter "output_clock_frequency11" = "0 MHz"
    Info (12134): Parameter "phase_shift11" = "0 ps"
    Info (12134): Parameter "duty_cycle11" = "50"
    Info (12134): Parameter "output_clock_frequency12" = "0 MHz"
    Info (12134): Parameter "phase_shift12" = "0 ps"
    Info (12134): Parameter "duty_cycle12" = "50"
    Info (12134): Parameter "output_clock_frequency13" = "0 MHz"
    Info (12134): Parameter "phase_shift13" = "0 ps"
    Info (12134): Parameter "duty_cycle13" = "50"
    Info (12134): Parameter "output_clock_frequency14" = "0 MHz"
    Info (12134): Parameter "phase_shift14" = "0 ps"
    Info (12134): Parameter "duty_cycle14" = "50"
    Info (12134): Parameter "output_clock_frequency15" = "0 MHz"
    Info (12134): Parameter "phase_shift15" = "0 ps"
    Info (12134): Parameter "duty_cycle15" = "50"
    Info (12134): Parameter "output_clock_frequency16" = "0 MHz"
    Info (12134): Parameter "phase_shift16" = "0 ps"
    Info (12134): Parameter "duty_cycle16" = "50"
    Info (12134): Parameter "output_clock_frequency17" = "0 MHz"
    Info (12134): Parameter "phase_shift17" = "0 ps"
    Info (12134): Parameter "duty_cycle17" = "50"
    Info (12134): Parameter "pll_type" = "Cyclone V"
    Info (12134): Parameter "pll_subtype" = "DPS"
    Info (12134): Parameter "m_cnt_hi_div" = "4"
    Info (12134): Parameter "m_cnt_lo_div" = "4"
    Info (12134): Parameter "n_cnt_hi_div" = "256"
    Info (12134): Parameter "n_cnt_lo_div" = "256"
    Info (12134): Parameter "m_cnt_bypass_en" = "false"
    Info (12134): Parameter "n_cnt_bypass_en" = "true"
    Info (12134): Parameter "m_cnt_odd_div_duty_en" = "false"
    Info (12134): Parameter "n_cnt_odd_div_duty_en" = "false"
    Info (12134): Parameter "c_cnt_hi_div0" = "4"
    Info (12134): Parameter "c_cnt_lo_div0" = "4"
    Info (12134): Parameter "c_cnt_prst0" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst0" = "0"
    Info (12134): Parameter "c_cnt_in_src0" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en0" = "false"
    Info (12134): Parameter "c_cnt_odd_div_duty_en0" = "false"
    Info (12134): Parameter "c_cnt_hi_div1" = "4"
    Info (12134): Parameter "c_cnt_lo_div1" = "4"
    Info (12134): Parameter "c_cnt_prst1" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst1" = "0"
    Info (12134): Parameter "c_cnt_in_src1" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en1" = "false"
    Info (12134): Parameter "c_cnt_odd_div_duty_en1" = "false"
    Info (12134): Parameter "c_cnt_hi_div2" = "4"
    Info (12134): Parameter "c_cnt_lo_div2" = "4"
    Info (12134): Parameter "c_cnt_prst2" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst2" = "0"
    Info (12134): Parameter "c_cnt_in_src2" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en2" = "false"
    Info (12134): Parameter "c_cnt_odd_div_duty_en2" = "false"
    Info (12134): Parameter "c_cnt_hi_div3" = "4"
    Info (12134): Parameter "c_cnt_lo_div3" = "4"
    Info (12134): Parameter "c_cnt_prst3" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst3" = "0"
    Info (12134): Parameter "c_cnt_in_src3" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en3" = "false"
    Info (12134): Parameter "c_cnt_odd_div_duty_en3" = "false"
    Info (12134): Parameter "c_cnt_hi_div4" = "4"
    Info (12134): Parameter "c_cnt_lo_div4" = "4"
    Info (12134): Parameter "c_cnt_prst4" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst4" = "0"
    Info (12134): Parameter "c_cnt_in_src4" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en4" = "false"
    Info (12134): Parameter "c_cnt_odd_div_duty_en4" = "false"
    Info (12134): Parameter "c_cnt_hi_div5" = "1"
    Info (12134): Parameter "c_cnt_lo_div5" = "1"
    Info (12134): Parameter "c_cnt_prst5" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst5" = "0"
    Info (12134): Parameter "c_cnt_in_src5" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en5" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en5" = "false"
    Info (12134): Parameter "c_cnt_hi_div6" = "1"
    Info (12134): Parameter "c_cnt_lo_div6" = "1"
    Info (12134): Parameter "c_cnt_prst6" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst6" = "0"
    Info (12134): Parameter "c_cnt_in_src6" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en6" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en6" = "false"
    Info (12134): Parameter "c_cnt_hi_div7" = "1"
    Info (12134): Parameter "c_cnt_lo_div7" = "1"
    Info (12134): Parameter "c_cnt_prst7" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst7" = "0"
    Info (12134): Parameter "c_cnt_in_src7" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en7" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en7" = "false"
    Info (12134): Parameter "c_cnt_hi_div8" = "1"
    Info (12134): Parameter "c_cnt_lo_div8" = "1"
    Info (12134): Parameter "c_cnt_prst8" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst8" = "0"
    Info (12134): Parameter "c_cnt_in_src8" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en8" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en8" = "false"
    Info (12134): Parameter "c_cnt_hi_div9" = "1"
    Info (12134): Parameter "c_cnt_lo_div9" = "1"
    Info (12134): Parameter "c_cnt_prst9" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst9" = "0"
    Info (12134): Parameter "c_cnt_in_src9" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en9" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en9" = "false"
    Info (12134): Parameter "c_cnt_hi_div10" = "1"
    Info (12134): Parameter "c_cnt_lo_div10" = "1"
    Info (12134): Parameter "c_cnt_prst10" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst10" = "0"
    Info (12134): Parameter "c_cnt_in_src10" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en10" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en10" = "false"
    Info (12134): Parameter "c_cnt_hi_div11" = "1"
    Info (12134): Parameter "c_cnt_lo_div11" = "1"
    Info (12134): Parameter "c_cnt_prst11" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst11" = "0"
    Info (12134): Parameter "c_cnt_in_src11" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en11" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en11" = "false"
    Info (12134): Parameter "c_cnt_hi_div12" = "1"
    Info (12134): Parameter "c_cnt_lo_div12" = "1"
    Info (12134): Parameter "c_cnt_prst12" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst12" = "0"
    Info (12134): Parameter "c_cnt_in_src12" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en12" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en12" = "false"
    Info (12134): Parameter "c_cnt_hi_div13" = "1"
    Info (12134): Parameter "c_cnt_lo_div13" = "1"
    Info (12134): Parameter "c_cnt_prst13" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst13" = "0"
    Info (12134): Parameter "c_cnt_in_src13" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en13" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en13" = "false"
    Info (12134): Parameter "c_cnt_hi_div14" = "1"
    Info (12134): Parameter "c_cnt_lo_div14" = "1"
    Info (12134): Parameter "c_cnt_prst14" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst14" = "0"
    Info (12134): Parameter "c_cnt_in_src14" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en14" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en14" = "false"
    Info (12134): Parameter "c_cnt_hi_div15" = "1"
    Info (12134): Parameter "c_cnt_lo_div15" = "1"
    Info (12134): Parameter "c_cnt_prst15" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst15" = "0"
    Info (12134): Parameter "c_cnt_in_src15" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en15" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en15" = "false"
    Info (12134): Parameter "c_cnt_hi_div16" = "1"
    Info (12134): Parameter "c_cnt_lo_div16" = "1"
    Info (12134): Parameter "c_cnt_prst16" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst16" = "0"
    Info (12134): Parameter "c_cnt_in_src16" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en16" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en16" = "false"
    Info (12134): Parameter "c_cnt_hi_div17" = "1"
    Info (12134): Parameter "c_cnt_lo_div17" = "1"
    Info (12134): Parameter "c_cnt_prst17" = "1"
    Info (12134): Parameter "c_cnt_ph_mux_prst17" = "0"
    Info (12134): Parameter "c_cnt_in_src17" = "ph_mux_clk"
    Info (12134): Parameter "c_cnt_bypass_en17" = "true"
    Info (12134): Parameter "c_cnt_odd_div_duty_en17" = "false"
    Info (12134): Parameter "pll_vco_div" = "2"
    Info (12134): Parameter "pll_cp_current" = "20"
    Info (12134): Parameter "pll_bwctrl" = "4000"
    Info (12134): Parameter "pll_output_clk_frequency" = "320.0 MHz"
    Info (12134): Parameter "pll_fractional_division" = "1"
    Info (12134): Parameter "mimic_fbclk_type" = "gclk"
    Info (12134): Parameter "pll_fbclk_mux_1" = "glb"
    Info (12134): Parameter "pll_fbclk_mux_2" = "fb_1"
    Info (12134): Parameter "pll_m_cnt_in_src" = "ph_mux_clk"
    Info (12134): Parameter "pll_slf_rst" = "false"
Info (12128): Elaborating entity "dps_extra_kick" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 768
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 768
Info (12128): Elaborating entity "dprio_init" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 783
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dprio_init:dprio_init_inst", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 783
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1960
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1960
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1971
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1971
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1982
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1982
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1993
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 1993
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 2004
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 2004
Info (12128): Elaborating entity "altera_cyclonev_pll" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 2223
Warning (10034): Output port "extclk" at altera_cyclonev_pll.v(631) has no driver File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 631
Warning (10034): Output port "clkout[0]" at altera_cyclonev_pll.v(636) has no driver File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 636
Warning (10034): Output port "loaden" at altera_cyclonev_pll.v(640) has no driver File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 640
Warning (10034): Output port "lvdsclk" at altera_cyclonev_pll.v(641) has no driver File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 641
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 2223
Info (12128): Elaborating entity "altera_cyclonev_pll_base" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 1152
Info (12131): Elaborated megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0", which is child of megafunction instantiation "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 1152
Info (12128): Elaborating entity "FTR_FINE_PHASE_SM" for hierarchy "FTR_CLK_WRAPPER:C_CLK_WRAPPER|FTR_FINE_PHASE_SM:C_PHASE_TUNE" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_CLK_WRAPPER.vhd Line: 134
Info (12128): Elaborating entity "UFP_WRAPPER_USB_UART" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 392
Info (12128): Elaborating entity "USB_USB_Reader" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB" File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 202
Info (12128): Elaborating entity "USB_UC_PCLK" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK" File: J:/vhdl_db/trunk/lib/usb_usb/src/USB_USB_Reader.vhd Line: 87
Info (12128): Elaborating entity "altddio_out" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component" File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 60
Info (12130): Elaborated megafunction instantiation "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component" File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 60
Info (12133): Instantiated megafunction "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component" with the following parameter: File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 60
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "extend_oe_disable" = "OFF"
    Info (12134): Parameter "invert_output" = "OFF"
    Info (12134): Parameter "oe_reg" = "UNREGISTERED"
    Info (12134): Parameter "power_up_high" = "OFF"
    Info (12134): Parameter "width" = "1"
    Info (12134): Parameter "lpm_hint" = "UNUSED"
    Info (12134): Parameter "lpm_type" = "altddio_out"
Info (12021): Found 1 design units, including 1 entities, in source file db/ddio_out_b2j.tdf
    Info (12023): Found entity 1: ddio_out_b2j File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/ddio_out_b2j.tdf Line: 27
Info (12128): Elaborating entity "ddio_out_b2j" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altddio_out.tdf Line: 100
Info (12128): Elaborating entity "USB_L2_TX_FIFO" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX" File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 239
Info (12128): Elaborating entity "dcfifo" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd Line: 104
Info (12130): Elaborated megafunction instantiation "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd Line: 104
Info (12133): Instantiated megafunction "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component" with the following parameter: File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd Line: 104
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "64"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "33"
    Info (12134): Parameter "lpm_widthu" = "6"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_85n1.tdf
    Info (12023): Found entity 1: dcfifo_85n1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_85n1.tdf Line: 40
Info (12128): Elaborating entity "dcfifo_85n1" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf Line: 190
Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_e9b.tdf
    Info (12023): Found entity 1: a_gray2bin_e9b File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_gray2bin_e9b.tdf Line: 22
Info (12128): Elaborating entity "a_gray2bin_e9b" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_gray2bin_e9b:rdptr_g_gray2bin" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_85n1.tdf Line: 54
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_bg6.tdf
    Info (12023): Found entity 1: a_graycounter_bg6 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_bg6.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_bg6" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_bg6:rdptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_85n1.tdf Line: 58
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_7ub.tdf
    Info (12023): Found entity 1: a_graycounter_7ub File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_7ub.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_7ub" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_7ub:wrptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_85n1.tdf Line: 59
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_cia1.tdf
    Info (12023): Found entity 1: altsyncram_cia1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/altsyncram_cia1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_cia1" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|altsyncram_cia1:fifo_ram" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_85n1.tdf Line: 60
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_vu8.tdf
    Info (12023): Found entity 1: dffpipe_vu8 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_vu8.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_vu8" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:rs_brp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_85n1.tdf Line: 67
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_f9l.tdf
    Info (12023): Found entity 1: alt_synch_pipe_f9l File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_f9l.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_f9l" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_85n1.tdf Line: 69
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_0v8.tdf
    Info (12023): Found entity 1: dffpipe_0v8 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_0v8.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_0v8" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_f9l.tdf Line: 33
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_g9l.tdf
    Info (12023): Found entity 1: alt_synch_pipe_g9l File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_g9l.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_g9l" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_85n1.tdf Line: 72
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_1v8.tdf
    Info (12023): Found entity 1: dffpipe_1v8 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_1v8.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_1v8" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_g9l.tdf Line: 33
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_vu5.tdf
    Info (12023): Found entity 1: cmpr_vu5 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/cmpr_vu5.tdf Line: 22
Info (12128): Elaborating entity "cmpr_vu5" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|cmpr_vu5:rdempty_eq_comp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_85n1.tdf Line: 79
Info (12128): Elaborating entity "ser_crc_pol16_DIN16_D4_1a2eb" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC" File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 254
Info (12128): Elaborating entity "ser_crc" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd Line: 47
Info (12128): Elaborating entity "UFP_ENCODER_UART" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER" File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 268
Info (12128): Elaborating entity "UFP_DECODER" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER" File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 323
Info (12128): Elaborating entity "ser_uart_wrapper" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART" File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 385
Warning (10541): VHDL Signal Declaration warning at ser_uart_wrapper.vhd(75): used implicit default value for signal "sl_int_fifoRX_rd_usedw" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper.vhd Line: 75
Info (12128): Elaborating entity "ser_uart_wrapper32" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper.vhd Line: 305
Info (12128): Elaborating entity "ser_uart" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper32.vhd Line: 90
Info (12128): Elaborating entity "ser_uart_bdgen" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_bdgen:\g_dbgen:C_BDGEN" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart.vhd Line: 84
Info (12128): Elaborating entity "ser_uart_ser" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart.vhd Line: 115
Info (12128): Elaborating entity "ser_uart_deser" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart.vhd Line: 139
Info (12128): Elaborating entity "ser_data_5_bits_filter" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|ser_data_5_bits_filter:C_FILTER_SIN" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_deser.vhd Line: 83
Info (12128): Elaborating entity "SER_UART_FIFO_TX32" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper32.vhd Line: 119
Info (12128): Elaborating entity "dcfifo_mixed_widths" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd Line: 106
Info (12130): Elaborated megafunction instantiation "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd Line: 106
Info (12133): Instantiated megafunction "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component" with the following parameter: File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd Line: 106
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "64"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo_mixed_widths"
    Info (12134): Parameter "lpm_width" = "32"
    Info (12134): Parameter "lpm_widthu" = "6"
    Info (12134): Parameter "lpm_widthu_r" = "8"
    Info (12134): Parameter "lpm_width_r" = "8"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_8tq1.tdf
    Info (12023): Found entity 1: dcfifo_8tq1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_8tq1.tdf Line: 42
Info (12128): Elaborating entity "dcfifo_8tq1" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo_mixed_widths.tdf Line: 78
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_cu6.tdf
    Info (12023): Found entity 1: a_graycounter_cu6 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_cu6.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_cu6" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_cu6:rdptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_8tq1.tdf Line: 58
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_9cc.tdf
    Info (12023): Found entity 1: a_graycounter_9cc File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_9cc.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_9cc" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_9cc:wrptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_8tq1.tdf Line: 59
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_po91.tdf
    Info (12023): Found entity 1: altsyncram_po91 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/altsyncram_po91.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_po91" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|altsyncram_po91:fifo_ram" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_8tq1.tdf Line: 60
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_unl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_unl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_unl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_unl" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_8tq1.tdf Line: 65
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_fd9.tdf
    Info (12023): Found entity 1: dffpipe_fd9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_fd9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_fd9" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_unl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_ed9.tdf
    Info (12023): Found entity 1: dffpipe_ed9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_ed9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_ed9" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_brp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_8tq1.tdf Line: 66
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_vnl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_vnl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_vnl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_vnl" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_8tq1.tdf Line: 68
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_gd9.tdf
    Info (12023): Found entity 1: dffpipe_gd9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_gd9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_gd9" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_vnl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_osd.tdf
    Info (12023): Found entity 1: cntr_osd File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/cntr_osd.tdf Line: 27
Info (12128): Elaborating entity "cntr_osd" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|cntr_osd:cntr_b" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_8tq1.tdf Line: 74
Info (12128): Elaborating entity "SER_UART_FIFO_RX32" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper32.vhd Line: 134
Info (12128): Elaborating entity "dcfifo_mixed_widths" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd Line: 102
Info (12130): Elaborated megafunction instantiation "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd Line: 102
Info (12133): Instantiated megafunction "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component" with the following parameter: File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd Line: 102
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "256"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo_mixed_widths"
    Info (12134): Parameter "lpm_width" = "8"
    Info (12134): Parameter "lpm_widthu" = "8"
    Info (12134): Parameter "lpm_widthu_r" = "6"
    Info (12134): Parameter "lpm_width_r" = "32"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_a5q1.tdf
    Info (12023): Found entity 1: dcfifo_a5q1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_a5q1.tdf Line: 38
Info (12128): Elaborating entity "dcfifo_a5q1" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo_mixed_widths.tdf Line: 78
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_du6.tdf
    Info (12023): Found entity 1: a_graycounter_du6 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_du6.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_du6" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_du6:rdptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_a5q1.tdf Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_8cc.tdf
    Info (12023): Found entity 1: a_graycounter_8cc File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_8cc.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_8cc" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_8cc:wrptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_a5q1.tdf Line: 52
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_qo91.tdf
    Info (12023): Found entity 1: altsyncram_qo91 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/altsyncram_qo91.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_qo91" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|altsyncram_qo91:fifo_ram" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_a5q1.tdf Line: 53
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_0ol.tdf
    Info (12023): Found entity 1: alt_synch_pipe_0ol File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_0ol.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_0ol" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_a5q1.tdf Line: 57
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_hd9.tdf
    Info (12023): Found entity 1: dffpipe_hd9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_hd9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_hd9" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_0ol.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_1ol.tdf
    Info (12023): Found entity 1: alt_synch_pipe_1ol File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_1ol.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_1ol" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_a5q1.tdf Line: 58
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_id9.tdf
    Info (12023): Found entity 1: dffpipe_id9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_id9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_id9" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_1ol.tdf Line: 34
Info (12128): Elaborating entity "FTR_L2_FIFO" for hierarchy "FTR_L2_FIFO:C_L2_FIFO" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 480
Info (12128): Elaborating entity "dcfifo" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_FIFO.vhd Line: 108
Info (12130): Elaborated megafunction instantiation "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_FIFO.vhd Line: 108
Info (12133): Instantiated megafunction "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component" with the following parameter: File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L2_FIFO.vhd Line: 108
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "65536"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "33"
    Info (12134): Parameter "lpm_widthu" = "16"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_kvr1.tdf
    Info (12023): Found entity 1: dcfifo_kvr1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_kvr1.tdf Line: 40
Info (12128): Elaborating entity "dcfifo_kvr1" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf Line: 190
Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_vab.tdf
    Info (12023): Found entity 1: a_gray2bin_vab File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_gray2bin_vab.tdf Line: 22
Info (12128): Elaborating entity "a_gray2bin_vab" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_gray2bin_vab:rdptr_g_gray2bin" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_kvr1.tdf Line: 55
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_uv6.tdf
    Info (12023): Found entity 1: a_graycounter_uv6 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_uv6.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_uv6" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_uv6:rdptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_kvr1.tdf Line: 59
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_qdc.tdf
    Info (12023): Found entity 1: a_graycounter_qdc File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_qdc.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_qdc" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|a_graycounter_qdc:wrptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_kvr1.tdf Line: 60
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_29d1.tdf
    Info (12023): Found entity 1: altsyncram_29d1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/altsyncram_29d1.tdf Line: 31
Info (12128): Elaborating entity "altsyncram_29d1" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_kvr1.tdf Line: 61
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_417.tdf
    Info (12023): Found entity 1: decode_417 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/decode_417.tdf Line: 22
Info (12128): Elaborating entity "decode_417" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|decode_417:decode12" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/altsyncram_29d1.tdf Line: 48
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_2t7.tdf
    Info (12023): Found entity 1: mux_2t7 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/mux_2t7.tdf Line: 22
Info (12128): Elaborating entity "mux_2t7" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|altsyncram_29d1:fifo_ram|mux_2t7:mux13" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/altsyncram_29d1.tdf Line: 50
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_6f9.tdf
    Info (12023): Found entity 1: dffpipe_6f9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_6f9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_6f9" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|dffpipe_6f9:rs_brp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_kvr1.tdf Line: 68
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_ipl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_ipl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_ipl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_ipl" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_kvr1.tdf Line: 70
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_7f9.tdf
    Info (12023): Found entity 1: dffpipe_7f9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_7f9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_7f9" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_ipl:rs_dgwp|dffpipe_7f9:dffpipe15" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_ipl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_jpl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_jpl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_jpl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_jpl" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_kvr1.tdf Line: 73
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_8f9.tdf
    Info (12023): Found entity 1: dffpipe_8f9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_8f9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_8f9" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|alt_synch_pipe_jpl:ws_dgrp|dffpipe_8f9:dffpipe18" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_jpl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_g06.tdf
    Info (12023): Found entity 1: cmpr_g06 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/cmpr_g06.tdf Line: 22
Info (12128): Elaborating entity "cmpr_g06" for hierarchy "FTR_L2_FIFO:C_L2_FIFO|dcfifo:dcfifo_component|dcfifo_kvr1:auto_generated|cmpr_g06:rdempty_eq_comp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_kvr1.tdf Line: 80
Info (12128): Elaborating entity "FTR_REG_WRAPPER" for hierarchy "FTR_REG_WRAPPER:C_REGS" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 500
Info (12128): Elaborating entity "UFP_USER_SET_CONFIG" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_PHASE_USER_SET" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 90
Info (12128): Elaborating entity "UFP_USER_GET_CONFIG" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_PHASE_USER_GET" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 110
Info (12128): Elaborating entity "UFP_USER_SET_CONFIG" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_CONFIG_USER_SET" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 135
Info (12128): Elaborating entity "UFP_USER_GET_CONFIG" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_CONFIG_USER_GET" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 155
Info (12128): Elaborating entity "UFP_USER_SET_CONFIG" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SOFT_CNT_USER_SET" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 180
Info (12128): Elaborating entity "UFP_USER_GET_CONFIG" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_GET_CONFIG:C_SOFT_CNT_USER_GET" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 201
Info (12128): Elaborating entity "UFP_USER_SET_CONFIG" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_SET_CONFIG:C_SLOW_CMD_USER_SET" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 226
Info (12128): Elaborating entity "UFP_USER_SETGET_ACK" for hierarchy "FTR_REG_WRAPPER:C_REGS|UFP_USER_SETGET_ACK:C_GET_ACK" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_REG_WRAPPER.vhd Line: 248
Info (12128): Elaborating entity "FTR_FaserWrapper" for hierarchy "FTR_FaserWrapper:C_WRAPPER" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 535
Info (12128): Elaborating entity "FTR_L2_SM" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_L2_SM:C_L2_SM" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FaserWrapper.vhd Line: 196
Info (12128): Elaborating entity "FTR_RXDataPlaneManager" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FaserWrapper.vhd Line: 247
Info (12128): Elaborating entity "FTR_RXDataModuleManager" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_RXDataModuleManager:\C_RXDPM_LED:0:C_RXDMM_LED" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataPlaneManager.vhd Line: 80
Info (12128): Elaborating entity "FTR_L1_FIFO" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_RXDataPlaneManager.vhd Line: 139
Info (12128): Elaborating entity "dcfifo" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L1_FIFO.vhd Line: 108
Info (12130): Elaborated megafunction instantiation "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L1_FIFO.vhd Line: 108
Info (12133): Instantiated megafunction "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component" with the following parameter: File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_L1_FIFO.vhd Line: 108
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "2048"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "26"
    Info (12134): Parameter "lpm_widthu" = "11"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_jtr1.tdf
    Info (12023): Found entity 1: dcfifo_jtr1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_jtr1.tdf Line: 40
Info (12128): Elaborating entity "dcfifo_jtr1" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf Line: 190
Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_qab.tdf
    Info (12023): Found entity 1: a_gray2bin_qab File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_gray2bin_qab.tdf Line: 22
Info (12128): Elaborating entity "a_gray2bin_qab" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_gray2bin_qab:rdptr_g_gray2bin" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_jtr1.tdf Line: 55
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_pv6.tdf
    Info (12023): Found entity 1: a_graycounter_pv6 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_pv6.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_pv6" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_pv6:rdptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_jtr1.tdf Line: 59
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_ldc.tdf
    Info (12023): Found entity 1: a_graycounter_ldc File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/a_graycounter_ldc.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_ldc" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|a_graycounter_ldc:wrptr_g1p" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_jtr1.tdf Line: 60
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_t8d1.tdf
    Info (12023): Found entity 1: altsyncram_t8d1 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/altsyncram_t8d1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_t8d1" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|altsyncram_t8d1:fifo_ram" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_jtr1.tdf Line: 61
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf
    Info (12023): Found entity 1: dffpipe_qe9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_qe9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_qe9" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|dffpipe_qe9:rs_brp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_jtr1.tdf Line: 68
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_apl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_apl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_apl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_apl" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_jtr1.tdf Line: 70
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_re9.tdf
    Info (12023): Found entity 1: dffpipe_re9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_re9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_re9" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_apl:rs_dgwp|dffpipe_re9:dffpipe13" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_apl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_bpl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_bpl File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_bpl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_bpl" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_jtr1.tdf Line: 73
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_ve9.tdf
    Info (12023): Found entity 1: dffpipe_ve9 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dffpipe_ve9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_ve9" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|alt_synch_pipe_bpl:ws_dgrp|dffpipe_ve9:dffpipe16" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/alt_synch_pipe_bpl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_b06.tdf
    Info (12023): Found entity 1: cmpr_b06 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/cmpr_b06.tdf Line: 22
Info (12128): Elaborating entity "cmpr_b06" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_RXDataPlaneManager:C_RXDPM|FTR_L1_FIFO:\C_FIFO_LEDS:0:C_FIFO_LED|dcfifo:dcfifo_component|dcfifo_jtr1:auto_generated|cmpr_b06:rdempty_eq_comp" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/db/dcfifo_jtr1.tdf Line: 80
Info (12128): Elaborating entity "FTR_PlaneController" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_FaserWrapper.vhd Line: 280
Info (12128): Elaborating entity "FTR_PlaneControllerSM" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PlaneControllerSM:C_PC_SM" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneController.vhd Line: 104
Info (12128): Elaborating entity "FTR_PatchPanelControllerSM" for hierarchy "FTR_FaserWrapper:C_WRAPPER|FTR_PlaneController:C_PC|FTR_PatchPanelControllerSM:C_PP_Controller0" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_PlaneController.vhd Line: 160
Warning (12030): Port "extclk" on the entity instantiation of "cyclonev_pll" is connected to a signal of width 1. The formal width of the signal in the module is 2.  The extra bits will be left dangling without any fan-out logic. File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 2223
Warning (19016): Clock multiplexers are found and protected
    Warning (19017): Found clock multiplexer FTR_CLK_WRAPPER:C_CLK_WRAPPER|sl_int_sel_clk~0 File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_CLK_WRAPPER.vhd Line: 74
Warning (12241): 16 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Warning (13034): The following nodes have both tri-state and non-tri-state drivers
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[0]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[1]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[2]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[3]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[4]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[5]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[6]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[7]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[8]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[9]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[10]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[11]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[12]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[13]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[14]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[15]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[16]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[17]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[18]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[19]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[20]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[21]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[22]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[23]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[24]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[25]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[26]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[27]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[28]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[29]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[30]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[31]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
Warning (13032): The following tri-state nodes are fed by constants
    Warning (13033): The pin "x_IO_8A[0]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[1]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[2]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[3]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[4]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[5]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[6]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[7]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[8]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[9]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[10]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[11]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[12]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[13]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[14]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
    Warning (13033): The pin "x_IO_8A[15]" is fed by GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 52
Info (13000): Registers with preset signals will power-up high File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc.vhd Line: 148
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (13009): TRI or OPNDRN buffers permanently enabled
    Warning (13010): Node "x_UC_DQ[0]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[1]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[2]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[3]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[4]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[5]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[6]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[7]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[8]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[9]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[10]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[11]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[12]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[13]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[14]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[15]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[16]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[17]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[18]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[19]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[20]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[21]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[22]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[23]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[24]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[25]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[26]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[27]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[28]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[29]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[30]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
    Warning (13010): Node "x_UC_DQ[31]~synth" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 28
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "x_UC_SLRDn" is stuck at VCC File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 32
    Warning (13410): Pin "x_UC_SLOEn" is stuck at VCC File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 33
    Warning (13410): Pin "x_UC_A[0]" is stuck at GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 35
    Warning (13410): Pin "x_UC_A[1]" is stuck at GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 35
    Warning (13410): Pin "x_UC_UART_CTSn" is stuck at VCC File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 43
    Warning (13410): Pin "x_DAC_CS" is stuck at GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 47
    Warning (13410): Pin "x_DAC_SDI" is stuck at GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 48
    Warning (13410): Pin "x_DAC_SCK" is stuck at GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 49
    Warning (13410): Pin "x_NIM_OUT" is stuck at GND File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 198
Info (286030): Timing-Driven Synthesis is running
Info (17049): 50 registers lost all their fanouts during netlist optimizations.
Info (17016): Found the following redundant logic cells in design
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0|combout" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v Line: 106
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1|combout" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v Line: 106
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2|combout" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v Line: 106
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3|combout" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v Line: 106
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4|combout" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v Line: 106
    Info (17048): Logic cell "sl_int_sct_tx_clk[0]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 248
    Info (17048): Logic cell "sl_int_sct_tx_clk[1]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 248
    Info (17048): Logic cell "sl_int_sel_clk" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 236
    Info (17048): Logic cell "sl_int_usb_ready" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 243
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[0]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[1]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[2]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[3]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[4]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[5]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[6]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[7]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[8]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[9]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[10]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[11]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[12]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[13]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[14]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|dps_writedata[15]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 407
    Info (17048): Logic cell "sl_int_sct_rx_clk[0]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 249
    Info (17048): Logic cell "sl_int_sct_rx_clk[1]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 249
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|cntsel_temp[0]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 424
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|cntsel_temp[1]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 424
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|cntsel_temp[2]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 424
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|cntsel_temp[3]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 424
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|cntsel_temp[4]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 424
    Info (17048): Logic cell "FTR_CLK_WRAPPER:C_CLK_WRAPPER|PLL_4K:C_PLL4|PLL_4K_0002:pll_4k_inst|altera_pll:altera_pll_i|gnd" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 426
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 115 node(s), including 33 DDIO, 2 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 46 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "x_UC_FLAGS[1]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 36
    Warning (15610): No output dependent on input pin "x_UC_FLAGS[2]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 36
    Warning (15610): No output dependent on input pin "x_UC_FLAGS[3]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 36
    Warning (15610): No output dependent on input pin "x_UC_UART_RTSn" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 42
    Warning (15610): No output dependent on input pin "x_5A_TXP1" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 128
    Warning (15610): No output dependent on input pin "x_5A_TXN1" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 129
    Warning (15610): No output dependent on input pin "x_5A_RXP6" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 130
    Warning (15610): No output dependent on input pin "x_5A_RXN6" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 131
    Warning (15610): No output dependent on input pin "x_5A_RXP8" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 132
    Warning (15610): No output dependent on input pin "x_5A_RXN8" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 133
    Warning (15610): No output dependent on input pin "x_5A_RXP4" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 134
    Warning (15610): No output dependent on input pin "x_5A_RXN4" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 135
    Warning (15610): No output dependent on input pin "x_5A_TXP7" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 136
    Warning (15610): No output dependent on input pin "x_5A_TXN7" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 137
    Warning (15610): No output dependent on input pin "x_5A_RXN2" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 138
    Warning (15610): No output dependent on input pin "x_7A_RXN1" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 141
    Warning (15610): No output dependent on input pin "x_7A_RXP1" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 142
    Warning (15610): No output dependent on input pin "x_7A_RXP5" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 143
    Warning (15610): No output dependent on input pin "x_7A_RXN5" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 144
    Warning (15610): No output dependent on input pin "x_7A_TXP8" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 145
    Warning (15610): No output dependent on input pin "x_7A_TXN8" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 146
    Warning (15610): No output dependent on input pin "x_7A_RXP9" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 147
    Warning (15610): No output dependent on input pin "x_7A_TXP2" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 150
    Warning (15610): No output dependent on input pin "x_7A_TXN2" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 151
    Warning (15610): No output dependent on input pin "x_7A_RXP3" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 152
    Warning (15610): No output dependent on input pin "x_7A_RXN3" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 153
    Warning (15610): No output dependent on input pin "x_7A_TXP4" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 154
    Warning (15610): No output dependent on input pin "x_7A_TXN4" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 155
    Warning (15610): No output dependent on input pin "x_7A_TXP6" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 156
    Warning (15610): No output dependent on input pin "x_7A_TXN6" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 157
    Warning (15610): No output dependent on input pin "x_7A_TXP10" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 160
    Warning (15610): No output dependent on input pin "x_7A_TXN10" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 161
    Warning (15610): No output dependent on input pin "x_7A_RXP11" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 162
    Warning (15610): No output dependent on input pin "x_7A_RXN11" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 163
    Warning (15610): No output dependent on input pin "x_7A_TXP12" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 164
    Warning (15610): No output dependent on input pin "x_7A_TXN12" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 165
    Warning (15610): No output dependent on input pin "x_7A_RXP33" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 177
    Warning (15610): No output dependent on input pin "x_7A_RXN33" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 178
    Warning (15610): No output dependent on input pin "x_8A_TXP54" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 185
    Warning (15610): No output dependent on input pin "x_8A_TXN54" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 186
    Warning (15610): No output dependent on input pin "x_8A_TXP56" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 187
    Warning (15610): No output dependent on input pin "x_8A_RXP55" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 192
    Warning (15610): No output dependent on input pin "x_8A_RXN55" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 193
    Warning (15610): No output dependent on input pin "x_8A_TXN56" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 194
    Warning (15610): No output dependent on input pin "x_NIM_IN[0]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 199
    Warning (15610): No output dependent on input pin "x_NIM_IN[1]" File: J:/vhdl_db/trunk/projets/FTR_FaserTrackerReadout/src/FTR_TOP.vhd Line: 199
Info (21057): Implemented 9605 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 74 input pins
    Info (21059): Implemented 80 output pins
    Info (21060): Implemented 49 bidirectional pins
    Info (21061): Implemented 8630 logic cells
    Info (21064): Implemented 729 RAM segments
    Info (21065): Implemented 2 PLLs
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 155 warnings
    Info: Peak virtual memory: 5047 megabytes
    Info: Processing ended: Thu Nov 26 13:16:51 2020
    Info: Elapsed time: 00:00:44
    Info: Total CPU time (on all processors): 00:00:54


