Analysis & Synthesis report for HFRB_GPIO_TOP
Tue Jun 23 15:32:34 2020
Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis IP Cores Summary
 10. State Machine - |HFRB_GPIO_TOP|HFRB_GPIO_RX_SM:C_GPIO_RX0|sl_int_state
 11. State Machine - |HFRB_GPIO_TOP|USB_USB_Reader:C_USB|sl_int_state
 12. State Machine - |HFRB_GPIO_TOP|USB_USB_Reader:C_USB|sl_int_start_state
 13. Registers Protected by Synthesis
 14. General Register Statistics
 15. Inverted Register Statistics
 16. Multiplexer Restructuring Statistics (Restructuring Performed)
 17. Source assignments for Top-level Entity: |HFRB_GPIO_TOP
 18. Source assignments for USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component
 19. Source assignments for USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
 20. Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component
 21. Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated
 22. Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|a_graycounter_oh6:rdptr_g1p
 23. Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|a_graycounter_kvb:wrptr_g1p
 24. Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|altsyncram_6la1:fifo_ram
 25. Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|dffpipe_c09:rs_brp
 26. Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|dffpipe_c09:rs_bwp
 27. Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp
 28. Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13
 29. Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp
 30. Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16
 31. Parameter Settings for User Entity Instance: PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i
 32. Parameter Settings for User Entity Instance: USB_USB_Reader:C_USB
 33. Parameter Settings for User Entity Instance: USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component
 34. Parameter Settings for User Entity Instance: HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component
 35. Parameter Settings for User Entity Instance: HFRB_GPIO_RX_SM:C_GPIO_RX0
 36. dcfifo Parameter Settings by Entity Instance
 37. Port Connectivity Checks: "USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK"
 38. Port Connectivity Checks: "USB_USB_Reader:C_USB"
 39. Port Connectivity Checks: "PLL_MAIN:C_PLL"
 40. Post-Synthesis Netlist Statistics for Top Partition
 41. Elapsed Time Per Partition
 42. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2018  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details.



+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                      ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status     ; Successful - Tue Jun 23 15:32:34 2020           ;
; Quartus Prime Version           ; 18.0.0 Build 614 04/24/2018 SJ Standard Edition ;
; Revision Name                   ; HFRB_GPIO_TOP                                   ;
; Top-level Entity Name           ; HFRB_GPIO_TOP                                   ;
; Family                          ; Cyclone V                                       ;
; Logic utilization (in ALMs)     ; N/A                                             ;
; Total registers                 ; 237                                             ;
; Total pins                      ; 204                                             ;
; Total virtual pins              ; 0                                               ;
; Total block memory bits         ; 135,168                                         ;
; Total DSP Blocks                ; 0                                               ;
; Total HSSI RX PCSs              ; 0                                               ;
; Total HSSI PMA RX Deserializers ; 0                                               ;
; Total HSSI TX PCSs              ; 0                                               ;
; Total HSSI PMA TX Serializers   ; 0                                               ;
; Total PLLs                      ; 1                                               ;
; Total DLLs                      ; 0                                               ;
+---------------------------------+-------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                             ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                          ; Setting            ; Default Value      ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                          ; 5CEBA7F23C8        ;                    ;
; Top-level entity name                                                           ; HFRB_GPIO_TOP      ; HFRB_GPIO_TOP      ;
; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
; VHDL Show LMF Mapping Messages                                                  ; Off                ;                    ;
; VHDL Version                                                                    ; VHDL_2008          ; VHDL_1993          ;
; Use smart compilation                                                           ; Off                ; Off                ;
; Enable parallel Assembler and Timing Analyzer during compilation                ; On                 ; On                 ;
; Enable compact report table                                                     ; Off                ; Off                ;
; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
; Preserve fewer node names                                                       ; On                 ; On                 ;
; Intel FPGA IP Evaluation Mode                                                   ; Enable             ; Enable             ;
; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
; State Machine Processing                                                        ; Auto               ; Auto               ;
; Safe State Machine                                                              ; Off                ; Off                ;
; Extract Verilog State Machines                                                  ; On                 ; On                 ;
; Extract VHDL State Machines                                                     ; On                 ; On                 ;
; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
; Parallel Synthesis                                                              ; On                 ; On                 ;
; DSP Block Balancing                                                             ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                              ; On                 ; On                 ;
; Power-Up Don't Care                                                             ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
; Remove Duplicate Registers                                                      ; On                 ; On                 ;
; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
; Optimization Technique                                                          ; Balanced           ; Balanced           ;
; Carry Chain Length                                                              ; 70                 ; 70                 ;
; Auto Carry Chains                                                               ; On                 ; On                 ;
; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
; Auto ROM Replacement                                                            ; On                 ; On                 ;
; Auto RAM Replacement                                                            ; On                 ; On                 ;
; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
; Strict RAM Replacement                                                          ; Off                ; Off                ;
; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                           ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
; Report Parameter Settings                                                       ; On                 ; On                 ;
; Report Source Assignments                                                       ; On                 ; On                 ;
; Report Connectivity Checks                                                      ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
; Power Optimization During Synthesis                                             ; Normal compilation ; Normal compilation ;
; HDL message level                                                               ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                            ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
; Block Design Naming                                                             ; Auto               ; Auto               ;
; SDC constraint protection                                                       ; Off                ; Off                ;
; Synthesis Effort                                                                ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
+---------------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   0.0%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                         ;
+--------------------------------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------------+----------+
; File Name with User-Entered Path                       ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                              ; Library  ;
+--------------------------------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------------+----------+
; ../../../../lib/u_util/exp/u_size.vhd                  ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/u_util/exp/u_size.vhd                                                ;          ;
; ../../../../lib/usb_usb/exp/USB_USB.vhd                ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/usb_usb/exp/USB_USB.vhd                                              ;          ;
; ../../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                               ;          ;
; ../../../../lib/usb_usb/src/USB_USB_Reader.vhd         ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/usb_usb/src/USB_USB_Reader.vhd                                       ;          ;
; src/HFRB_GPIO_GLOBAL_CONST.vhd                         ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_GLOBAL_CONST.vhd ;          ;
; src/PLL_MAIN.vhd                                       ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/PLL_MAIN.vhd               ; PLL_MAIN ;
; src/PLL_MAIN/PLL_MAIN_0002.v                           ; yes             ; User Verilog HDL File        ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/PLL_MAIN/PLL_MAIN_0002.v   ; PLL_MAIN ;
; ../../src/HFRB_GPIO_RX_SM.vhd                          ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/src/HFRB_GPIO_RX_SM.vhd                 ;          ;
; src/HFRB_GPIO_TOP.vhd                                  ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd          ;          ;
; src/HFRB_USB_FIFO.vhd                                  ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_USB_FIFO.vhd          ;          ;
; altera_pll.v                                           ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v                            ;          ;
; altddio_out.tdf                                        ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altddio_out.tdf                         ;          ;
; aglobal180.inc                                         ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/aglobal180.inc                          ;          ;
; stratix_ddio.inc                                       ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/stratix_ddio.inc                        ;          ;
; cyclone_ddio.inc                                       ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/cyclone_ddio.inc                        ;          ;
; lpm_mux.inc                                            ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_mux.inc                             ;          ;
; stratix_lcell.inc                                      ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/stratix_lcell.inc                       ;          ;
; db/ddio_out_b2j.tdf                                    ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/ddio_out_b2j.tdf            ;          ;
; dcfifo.tdf                                             ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf                              ;          ;
; lpm_counter.inc                                        ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_counter.inc                         ;          ;
; lpm_add_sub.inc                                        ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_add_sub.inc                         ;          ;
; altdpram.inc                                           ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altdpram.inc                            ;          ;
; a_graycounter.inc                                      ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_graycounter.inc                       ;          ;
; a_fefifo.inc                                           ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fefifo.inc                            ;          ;
; a_gray2bin.inc                                         ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_gray2bin.inc                          ;          ;
; dffpipe.inc                                            ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/dffpipe.inc                             ;          ;
; alt_sync_fifo.inc                                      ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/alt_sync_fifo.inc                       ;          ;
; lpm_compare.inc                                        ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_compare.inc                         ;          ;
; altsyncram_fifo.inc                                    ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram_fifo.inc                     ;          ;
; db/dcfifo_qhm1.tdf                                     ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dcfifo_qhm1.tdf             ;          ;
; db/a_gray2bin_rab.tdf                                  ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/a_gray2bin_rab.tdf          ;          ;
; db/a_graycounter_oh6.tdf                               ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/a_graycounter_oh6.tdf       ;          ;
; db/a_graycounter_kvb.tdf                               ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/a_graycounter_kvb.tdf       ;          ;
; db/altsyncram_6la1.tdf                                 ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/altsyncram_6la1.tdf         ;          ;
; db/dffpipe_c09.tdf                                     ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dffpipe_c09.tdf             ;          ;
; db/alt_synch_pipe_sal.tdf                              ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/alt_synch_pipe_sal.tdf      ;          ;
; db/dffpipe_d09.tdf                                     ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dffpipe_d09.tdf             ;          ;
; db/alt_synch_pipe_tal.tdf                              ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/alt_synch_pipe_tal.tdf      ;          ;
; db/dffpipe_e09.tdf                                     ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dffpipe_e09.tdf             ;          ;
; db/cmpr_c06.tdf                                        ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/cmpr_c06.tdf                ;          ;
+--------------------------------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------------+----------+


+---------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                   ;
+---------------------------------------------+-----------------+
; Resource                                    ; Usage           ;
+---------------------------------------------+-----------------+
; Estimate of Logic utilization (ALMs needed) ; 136             ;
;                                             ;                 ;
; Combinational ALUT usage for logic          ; 121             ;
;     -- 7 input functions                    ; 0               ;
;     -- 6 input functions                    ; 37              ;
;     -- 5 input functions                    ; 18              ;
;     -- 4 input functions                    ; 17              ;
;     -- <=3 input functions                  ; 49              ;
;                                             ;                 ;
; Dedicated logic registers                   ; 235             ;
;                                             ;                 ;
; I/O pins                                    ; 204             ;
; I/O registers                               ; 2               ;
; Total MLAB memory bits                      ; 0               ;
; Total block memory bits                     ; 135168          ;
;                                             ;                 ;
; Total DSP Blocks                            ; 0               ;
;                                             ;                 ;
; Total PLLs                                  ; 1               ;
;     -- PLLs                                 ; 1               ;
;                                             ;                 ;
; Maximum fan-out node                        ; sl_int_main_clk ;
; Maximum fan-out                             ; 155             ;
; Total fan-out                               ; 2342            ;
; Average fan-out                             ; 2.76            ;
+---------------------------------------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                 ;
+----------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------+--------------------+--------------+
; Compilation Hierarchy Node                   ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                     ; Entity Name        ; Library Name ;
+----------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------+--------------------+--------------+
; |HFRB_GPIO_TOP                               ; 121 (4)             ; 235 (0)                   ; 135168            ; 0          ; 204  ; 0            ; |HFRB_GPIO_TOP                                                                                                                          ; HFRB_GPIO_TOP      ; work         ;
;    |HFRB_GPIO_RX_SM:C_GPIO_RX0|              ; 22 (22)             ; 47 (47)                   ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|HFRB_GPIO_RX_SM:C_GPIO_RX0                                                                                               ; HFRB_GPIO_RX_SM    ; work         ;
;    |HFRB_USB_FIFO:C_FIFO|                    ; 57 (0)              ; 125 (0)                   ; 135168            ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|HFRB_USB_FIFO:C_FIFO                                                                                                     ; HFRB_USB_FIFO      ; work         ;
;       |dcfifo:dcfifo_component|              ; 57 (0)              ; 125 (0)                   ; 135168            ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component                                                                             ; dcfifo             ; work         ;
;          |dcfifo_qhm1:auto_generated|        ; 57 (5)              ; 125 (39)                  ; 135168            ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated                                                  ; dcfifo_qhm1        ; work         ;
;             |a_graycounter_kvb:wrptr_g1p|    ; 19 (19)             ; 17 (17)                   ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|a_graycounter_kvb:wrptr_g1p                      ; a_graycounter_kvb  ; work         ;
;             |a_graycounter_oh6:rdptr_g1p|    ; 22 (22)             ; 17 (17)                   ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|a_graycounter_oh6:rdptr_g1p                      ; a_graycounter_oh6  ; work         ;
;             |alt_synch_pipe_sal:rs_dgwp|     ; 0 (0)               ; 26 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp                       ; alt_synch_pipe_sal ; work         ;
;                |dffpipe_d09:dffpipe13|       ; 0 (0)               ; 26 (26)                   ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13 ; dffpipe_d09        ; work         ;
;             |alt_synch_pipe_tal:ws_dgrp|     ; 0 (0)               ; 26 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp                       ; alt_synch_pipe_tal ; work         ;
;                |dffpipe_e09:dffpipe16|       ; 0 (0)               ; 26 (26)                   ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16 ; dffpipe_e09        ; work         ;
;             |altsyncram_6la1:fifo_ram|       ; 0 (0)               ; 0 (0)                     ; 135168            ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|altsyncram_6la1:fifo_ram                         ; altsyncram_6la1    ; work         ;
;             |cmpr_c06:rdempty_eq_comp|       ; 6 (6)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|cmpr_c06:rdempty_eq_comp                         ; cmpr_c06           ; work         ;
;             |cmpr_c06:wrfull_eq_comp|        ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|cmpr_c06:wrfull_eq_comp                          ; cmpr_c06           ; work         ;
;    |PLL_MAIN:C_PLL|                          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|PLL_MAIN:C_PLL                                                                                                           ; PLL_MAIN           ; pll_main     ;
;       |PLL_MAIN_0002:pll_main_inst|          ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst                                                                               ; PLL_MAIN_0002      ; PLL_MAIN     ;
;          |altera_pll:altera_pll_i|           ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i                                                       ; altera_pll         ; work         ;
;    |USB_USB_Reader:C_USB|                    ; 38 (38)             ; 63 (63)                   ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|USB_USB_Reader:C_USB                                                                                                     ; USB_USB_Reader     ; work         ;
;       |USB_UC_PCLK:C_UC_PCLK|                ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK                                                                               ; USB_UC_PCLK        ; work         ;
;          |altddio_out:ALTDDIO_OUT_component| ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component                                             ; altddio_out        ; work         ;
;             |ddio_out_b2j:auto_generated|    ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |HFRB_GPIO_TOP|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                 ; ddio_out_b2j       ; work         ;
+----------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------+--------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                  ;
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
; Name                                                                                                        ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF  ;
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|altsyncram_6la1:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 4096         ; 33           ; 4096         ; 33           ; 135168 ; None ;
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                                              ;
+--------+--------------+---------+--------------+--------------+-----------------------------------------------------------+--------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                                           ; IP Include File                                        ;
+--------+--------------+---------+--------------+--------------+-----------------------------------------------------------+--------------------------------------------------------+
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |HFRB_GPIO_TOP|HFRB_USB_FIFO:C_FIFO                       ; src/HFRB_USB_FIFO.vhd                                  ;
; Altera ; altera_pll   ; 18.0    ; N/A          ; N/A          ; |HFRB_GPIO_TOP|PLL_MAIN:C_PLL                             ; src/PLL_MAIN.vhd                                       ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |HFRB_GPIO_TOP|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK ; ../../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd ;
+--------+--------------+---------+--------------+--------------+-----------------------------------------------------------+--------------------------------------------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------+
; State Machine - |HFRB_GPIO_TOP|HFRB_GPIO_RX_SM:C_GPIO_RX0|sl_int_state                                                  ;
+---------------------------+---------------------------+-------------------+-------------------------+-------------------+
; Name                      ; sl_int_state.RECOVER_STOP ; sl_int_state.STOP ; sl_int_state.DATA_DESER ; sl_int_state.IDLE ;
+---------------------------+---------------------------+-------------------+-------------------------+-------------------+
; sl_int_state.IDLE         ; 0                         ; 0                 ; 0                       ; 0                 ;
; sl_int_state.DATA_DESER   ; 0                         ; 0                 ; 1                       ; 1                 ;
; sl_int_state.STOP         ; 0                         ; 1                 ; 0                       ; 1                 ;
; sl_int_state.RECOVER_STOP ; 1                         ; 0                 ; 0                       ; 1                 ;
+---------------------------+---------------------------+-------------------+-------------------------+-------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |HFRB_GPIO_TOP|USB_USB_Reader:C_USB|sl_int_state                                                                                             ;
+---------------------------+---------------------------+------------------------+------------------+-----------------+-------------------+--------------------+
; Name                      ; sl_int_state.WAIT_UC_FULL ; sl_int_state.CHECK_ZLP ; sl_int_state.ZLP ; sl_int_state.WR ; sl_int_state.IDLE ; sl_int_state.START ;
+---------------------------+---------------------------+------------------------+------------------+-----------------+-------------------+--------------------+
; sl_int_state.START        ; 0                         ; 0                      ; 0                ; 0               ; 0                 ; 0                  ;
; sl_int_state.IDLE         ; 0                         ; 0                      ; 0                ; 0               ; 1                 ; 1                  ;
; sl_int_state.WR           ; 0                         ; 0                      ; 0                ; 1               ; 0                 ; 1                  ;
; sl_int_state.ZLP          ; 0                         ; 0                      ; 1                ; 0               ; 0                 ; 1                  ;
; sl_int_state.CHECK_ZLP    ; 0                         ; 1                      ; 0                ; 0               ; 0                 ; 1                  ;
; sl_int_state.WAIT_UC_FULL ; 1                         ; 0                      ; 0                ; 0               ; 0                 ; 1                  ;
+---------------------------+---------------------------+------------------------+------------------+-----------------+-------------------+--------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |HFRB_GPIO_TOP|USB_USB_Reader:C_USB|sl_int_start_state                                                                                                                             ;
+----------------------------+----------------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------------+
; Name                       ; sl_int_start_state.STARTED ; sl_int_start_state.START4 ; sl_int_start_state.START3 ; sl_int_start_state.START2 ; sl_int_start_state.START1 ; sl_int_start_state.START ;
+----------------------------+----------------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------------+
; sl_int_start_state.START   ; 0                          ; 0                         ; 0                         ; 0                         ; 0                         ; 0                        ;
; sl_int_start_state.START1  ; 0                          ; 0                         ; 0                         ; 0                         ; 1                         ; 1                        ;
; sl_int_start_state.START2  ; 0                          ; 0                         ; 0                         ; 1                         ; 0                         ; 1                        ;
; sl_int_start_state.START3  ; 0                          ; 0                         ; 1                         ; 0                         ; 0                         ; 1                        ;
; sl_int_start_state.START4  ; 0                          ; 1                         ; 0                         ; 0                         ; 0                         ; 1                        ;
; sl_int_start_state.STARTED ; 1                          ; 0                         ; 0                         ; 0                         ; 0                         ; 1                        ;
+----------------------------+----------------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis                                                                                                                                                                                                                     ;
+--------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name                                                                                                                        ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+--------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe18a[12] ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe18a[10] ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe18a[11] ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe18a[8]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe18a[9]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe18a[6]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe18a[7]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe18a[4]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe18a[5]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe18a[2]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe18a[3]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe18a[0]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe18a[1]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe17a[12] ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe17a[10] ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe17a[11] ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe17a[8]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe17a[9]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe17a[6]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe17a[7]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe17a[4]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe17a[5]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe17a[2]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe17a[3]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe17a[0]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16|dffe17a[1]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe15a[12] ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe15a[10] ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe15a[11] ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe15a[8]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe15a[9]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe15a[6]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe15a[7]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe15a[4]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe15a[5]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe15a[2]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe15a[3]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe15a[0]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe15a[1]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe14a[12] ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe14a[10] ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe14a[11] ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe14a[8]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe14a[9]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe14a[6]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe14a[7]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe14a[4]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe14a[5]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe14a[2]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe14a[3]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe14a[0]  ; yes                                                              ; yes                                        ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13|dffe14a[1]  ; yes                                                              ; yes                                        ;
; Total number of protected registers is 52                                                                                            ;                                                                  ;                                            ;
+--------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 235   ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 11    ;
; Number of registers using Asynchronous Clear ; 109   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 50    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                             ;
+----------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                              ; Fan out ;
+----------------------------------------------------------------------------------------------------------------+---------+
; USB_USB_Reader:C_USB|sl_int_wrn[1]                                                                             ; 1       ;
; USB_USB_Reader:C_USB|sl_int_pkendn                                                                             ; 1       ;
; USB_USB_Reader:C_USB|sl_int_startn[0]                                                                          ; 6       ;
; USB_USB_Reader:C_USB|sl_int_wrn[0]                                                                             ; 2       ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|a_graycounter_kvb:wrptr_g1p|counter8a0 ; 7       ;
; USB_USB_Reader:C_USB|sl_int_startn[1]                                                                          ; 1       ;
; USB_USB_Reader:C_USB|sl_int_uc_full                                                                            ; 12      ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|a_graycounter_oh6:rdptr_g1p|counter5a0 ; 11      ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|a_graycounter_kvb:wrptr_g1p|parity9    ; 5       ;
; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|a_graycounter_oh6:rdptr_g1p|parity6    ; 7       ;
; Total number of inverted registers = 10                                                                        ;         ;
+----------------------------------------------------------------------------------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |HFRB_GPIO_TOP|HFRB_GPIO_RX_SM:C_GPIO_RX0|x_state_g[0] ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |HFRB_GPIO_TOP|HFRB_GPIO_RX_SM:C_GPIO_RX0|x_fifo_error ;
; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |HFRB_GPIO_TOP|HFRB_GPIO_RX_SM:C_GPIO_RX0|Selector2    ;
; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |HFRB_GPIO_TOP|HFRB_GPIO_RX_SM:C_GPIO_RX0|Selector0    ;
; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |HFRB_GPIO_TOP|USB_USB_Reader:C_USB|Selector4          ;
; 12:1               ; 6 bits    ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; No         ; |HFRB_GPIO_TOP|USB_USB_Reader:C_USB|Selector11         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------+


+----------------------------------------------------------------+
; Source assignments for Top-level Entity: |HFRB_GPIO_TOP        ;
+------------------------------+-------+------+------------------+
; Assignment                   ; Value ; From ; To               ;
+------------------------------+-------+------+------------------+
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_main_clk  ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_main_clk  ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sl_int_usb_ready ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sl_int_usb_ready ;
+------------------------------+-------+------+------------------+


+-----------------------------------------------------------------------------------------------------+
; Source assignments for USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                   ;
+-------------------------+-------------+------+------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                    ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                        ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                        ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                  ;
+-------------------------+-------------+------+------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+----------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                               ;
+-----------------------------+---------+------+----------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                ;
+-----------------------------+---------+------+----------------------------------------------------------------------------------+


+---------------------------------------------------------------------+
; Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+--------------------+
; Assignment                      ; Value ; From ; To                 ;
+---------------------------------+-------+------+--------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                  ;
+---------------------------------+-------+------+--------------------+


+------------------------------------------------------------------------------------------------+
; Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated ;
+---------------------------------------+-------+------+-----------------------------------------+
; Assignment                            ; Value ; From ; To                                      ;
+---------------------------------------+-------+------+-----------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                       ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                       ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                       ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                       ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                 ;
+---------------------------------------+-------+------+-----------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|a_graycounter_oh6:rdptr_g1p ;
+----------------+-------+------+--------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                         ;
+----------------+-------+------+--------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                 ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                    ;
+----------------+-------+------+--------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|a_graycounter_kvb:wrptr_g1p ;
+----------------+-------+------+--------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                         ;
+----------------+-------+------+--------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                 ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                    ;
+----------------+-------+------+--------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|altsyncram_6la1:fifo_ram ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                        ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                         ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|dffpipe_c09:rs_brp ;
+---------------------------------+-------+------+------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                               ;
+---------------------------------+-------+------+------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                ;
+---------------------------------+-------+------+------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|dffpipe_c09:rs_bwp ;
+---------------------------------+-------+------+------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                               ;
+---------------------------------+-------+------+------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                ;
+---------------------------------+-------+------+------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp ;
+-----------------------------+------------------------+------+-------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                          ;
+-----------------------------+------------------------+------+-------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                           ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                           ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                           ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                           ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                           ;
+-----------------------------+------------------------+------+-------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                             ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                              ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp ;
+-----------------------------+------------------------+------+-------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                          ;
+-----------------------------+------------------------+------+-------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                           ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                           ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                           ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                           ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                           ;
+-----------------------------+------------------------+------+-------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                             ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                              ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i ;
+--------------------------------------+------------------------+-------------------------------------------------+
; Parameter Name                       ; Value                  ; Type                                            ;
+--------------------------------------+------------------------+-------------------------------------------------+
; reference_clock_frequency            ; 40.0 MHz               ; String                                          ;
; fractional_vco_multiplier            ; false                  ; String                                          ;
; pll_type                             ; General                ; String                                          ;
; pll_subtype                          ; General                ; String                                          ;
; number_of_clocks                     ; 2                      ; Signed Integer                                  ;
; operation_mode                       ; direct                 ; String                                          ;
; deserialization_factor               ; 4                      ; Signed Integer                                  ;
; data_rate                            ; 0                      ; Signed Integer                                  ;
; sim_additional_refclk_cycles_to_lock ; 0                      ; Signed Integer                                  ;
; output_clock_frequency0              ; 40.000000 MHz          ; String                                          ;
; phase_shift0                         ; 0 ps                   ; String                                          ;
; duty_cycle0                          ; 50                     ; Signed Integer                                  ;
; output_clock_frequency1              ; 32.000000 MHz          ; String                                          ;
; phase_shift1                         ; 0 ps                   ; String                                          ;
; duty_cycle1                          ; 50                     ; Signed Integer                                  ;
; output_clock_frequency2              ; 0 MHz                  ; String                                          ;
; phase_shift2                         ; 0 ps                   ; String                                          ;
; duty_cycle2                          ; 50                     ; Signed Integer                                  ;
; output_clock_frequency3              ; 0 MHz                  ; String                                          ;
; phase_shift3                         ; 0 ps                   ; String                                          ;
; duty_cycle3                          ; 50                     ; Signed Integer                                  ;
; output_clock_frequency4              ; 0 MHz                  ; String                                          ;
; phase_shift4                         ; 0 ps                   ; String                                          ;
; duty_cycle4                          ; 50                     ; Signed Integer                                  ;
; output_clock_frequency5              ; 0 MHz                  ; String                                          ;
; phase_shift5                         ; 0 ps                   ; String                                          ;
; duty_cycle5                          ; 50                     ; Signed Integer                                  ;
; output_clock_frequency6              ; 0 MHz                  ; String                                          ;
; phase_shift6                         ; 0 ps                   ; String                                          ;
; duty_cycle6                          ; 50                     ; Signed Integer                                  ;
; output_clock_frequency7              ; 0 MHz                  ; String                                          ;
; phase_shift7                         ; 0 ps                   ; String                                          ;
; duty_cycle7                          ; 50                     ; Signed Integer                                  ;
; output_clock_frequency8              ; 0 MHz                  ; String                                          ;
; phase_shift8                         ; 0 ps                   ; String                                          ;
; duty_cycle8                          ; 50                     ; Signed Integer                                  ;
; output_clock_frequency9              ; 0 MHz                  ; String                                          ;
; phase_shift9                         ; 0 ps                   ; String                                          ;
; duty_cycle9                          ; 50                     ; Signed Integer                                  ;
; output_clock_frequency10             ; 0 MHz                  ; String                                          ;
; phase_shift10                        ; 0 ps                   ; String                                          ;
; duty_cycle10                         ; 50                     ; Signed Integer                                  ;
; output_clock_frequency11             ; 0 MHz                  ; String                                          ;
; phase_shift11                        ; 0 ps                   ; String                                          ;
; duty_cycle11                         ; 50                     ; Signed Integer                                  ;
; output_clock_frequency12             ; 0 MHz                  ; String                                          ;
; phase_shift12                        ; 0 ps                   ; String                                          ;
; duty_cycle12                         ; 50                     ; Signed Integer                                  ;
; output_clock_frequency13             ; 0 MHz                  ; String                                          ;
; phase_shift13                        ; 0 ps                   ; String                                          ;
; duty_cycle13                         ; 50                     ; Signed Integer                                  ;
; output_clock_frequency14             ; 0 MHz                  ; String                                          ;
; phase_shift14                        ; 0 ps                   ; String                                          ;
; duty_cycle14                         ; 50                     ; Signed Integer                                  ;
; output_clock_frequency15             ; 0 MHz                  ; String                                          ;
; phase_shift15                        ; 0 ps                   ; String                                          ;
; duty_cycle15                         ; 50                     ; Signed Integer                                  ;
; output_clock_frequency16             ; 0 MHz                  ; String                                          ;
; phase_shift16                        ; 0 ps                   ; String                                          ;
; duty_cycle16                         ; 50                     ; Signed Integer                                  ;
; output_clock_frequency17             ; 0 MHz                  ; String                                          ;
; phase_shift17                        ; 0 ps                   ; String                                          ;
; duty_cycle17                         ; 50                     ; Signed Integer                                  ;
; clock_name_0                         ;                        ; String                                          ;
; clock_name_1                         ;                        ; String                                          ;
; clock_name_2                         ;                        ; String                                          ;
; clock_name_3                         ;                        ; String                                          ;
; clock_name_4                         ;                        ; String                                          ;
; clock_name_5                         ;                        ; String                                          ;
; clock_name_6                         ;                        ; String                                          ;
; clock_name_7                         ;                        ; String                                          ;
; clock_name_8                         ;                        ; String                                          ;
; clock_name_global_0                  ; false                  ; String                                          ;
; clock_name_global_1                  ; false                  ; String                                          ;
; clock_name_global_2                  ; false                  ; String                                          ;
; clock_name_global_3                  ; false                  ; String                                          ;
; clock_name_global_4                  ; false                  ; String                                          ;
; clock_name_global_5                  ; false                  ; String                                          ;
; clock_name_global_6                  ; false                  ; String                                          ;
; clock_name_global_7                  ; false                  ; String                                          ;
; clock_name_global_8                  ; false                  ; String                                          ;
; m_cnt_hi_div                         ; 1                      ; Signed Integer                                  ;
; m_cnt_lo_div                         ; 1                      ; Signed Integer                                  ;
; m_cnt_bypass_en                      ; false                  ; String                                          ;
; m_cnt_odd_div_duty_en                ; false                  ; String                                          ;
; n_cnt_hi_div                         ; 1                      ; Signed Integer                                  ;
; n_cnt_lo_div                         ; 1                      ; Signed Integer                                  ;
; n_cnt_bypass_en                      ; false                  ; String                                          ;
; n_cnt_odd_div_duty_en                ; false                  ; String                                          ;
; c_cnt_hi_div0                        ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div0                        ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en0                     ; false                  ; String                                          ;
; c_cnt_in_src0                        ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en0               ; false                  ; String                                          ;
; c_cnt_prst0                          ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst0                   ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div1                        ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div1                        ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en1                     ; false                  ; String                                          ;
; c_cnt_in_src1                        ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en1               ; false                  ; String                                          ;
; c_cnt_prst1                          ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst1                   ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div2                        ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div2                        ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en2                     ; false                  ; String                                          ;
; c_cnt_in_src2                        ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en2               ; false                  ; String                                          ;
; c_cnt_prst2                          ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst2                   ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div3                        ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div3                        ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en3                     ; false                  ; String                                          ;
; c_cnt_in_src3                        ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en3               ; false                  ; String                                          ;
; c_cnt_prst3                          ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst3                   ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div4                        ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div4                        ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en4                     ; false                  ; String                                          ;
; c_cnt_in_src4                        ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en4               ; false                  ; String                                          ;
; c_cnt_prst4                          ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst4                   ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div5                        ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div5                        ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en5                     ; false                  ; String                                          ;
; c_cnt_in_src5                        ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en5               ; false                  ; String                                          ;
; c_cnt_prst5                          ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst5                   ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div6                        ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div6                        ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en6                     ; false                  ; String                                          ;
; c_cnt_in_src6                        ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en6               ; false                  ; String                                          ;
; c_cnt_prst6                          ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst6                   ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div7                        ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div7                        ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en7                     ; false                  ; String                                          ;
; c_cnt_in_src7                        ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en7               ; false                  ; String                                          ;
; c_cnt_prst7                          ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst7                   ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div8                        ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div8                        ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en8                     ; false                  ; String                                          ;
; c_cnt_in_src8                        ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en8               ; false                  ; String                                          ;
; c_cnt_prst8                          ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst8                   ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div9                        ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div9                        ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en9                     ; false                  ; String                                          ;
; c_cnt_in_src9                        ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en9               ; false                  ; String                                          ;
; c_cnt_prst9                          ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst9                   ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div10                       ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div10                       ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en10                    ; false                  ; String                                          ;
; c_cnt_in_src10                       ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en10              ; false                  ; String                                          ;
; c_cnt_prst10                         ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst10                  ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div11                       ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div11                       ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en11                    ; false                  ; String                                          ;
; c_cnt_in_src11                       ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en11              ; false                  ; String                                          ;
; c_cnt_prst11                         ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst11                  ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div12                       ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div12                       ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en12                    ; false                  ; String                                          ;
; c_cnt_in_src12                       ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en12              ; false                  ; String                                          ;
; c_cnt_prst12                         ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst12                  ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div13                       ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div13                       ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en13                    ; false                  ; String                                          ;
; c_cnt_in_src13                       ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en13              ; false                  ; String                                          ;
; c_cnt_prst13                         ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst13                  ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div14                       ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div14                       ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en14                    ; false                  ; String                                          ;
; c_cnt_in_src14                       ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en14              ; false                  ; String                                          ;
; c_cnt_prst14                         ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst14                  ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div15                       ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div15                       ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en15                    ; false                  ; String                                          ;
; c_cnt_in_src15                       ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en15              ; false                  ; String                                          ;
; c_cnt_prst15                         ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst15                  ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div16                       ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div16                       ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en16                    ; false                  ; String                                          ;
; c_cnt_in_src16                       ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en16              ; false                  ; String                                          ;
; c_cnt_prst16                         ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst16                  ; 0                      ; Signed Integer                                  ;
; c_cnt_hi_div17                       ; 1                      ; Signed Integer                                  ;
; c_cnt_lo_div17                       ; 1                      ; Signed Integer                                  ;
; c_cnt_bypass_en17                    ; false                  ; String                                          ;
; c_cnt_in_src17                       ; ph_mux_clk             ; String                                          ;
; c_cnt_odd_div_duty_en17              ; false                  ; String                                          ;
; c_cnt_prst17                         ; 1                      ; Signed Integer                                  ;
; c_cnt_ph_mux_prst17                  ; 0                      ; Signed Integer                                  ;
; pll_vco_div                          ; 1                      ; Signed Integer                                  ;
; pll_slf_rst                          ; false                  ; String                                          ;
; pll_bw_sel                           ; low                    ; String                                          ;
; pll_output_clk_frequency             ; 0 MHz                  ; String                                          ;
; pll_cp_current                       ; 0                      ; Signed Integer                                  ;
; pll_bwctrl                           ; 0                      ; Signed Integer                                  ;
; pll_fractional_division              ; 1                      ; Signed Integer                                  ;
; pll_fractional_cout                  ; 24                     ; Signed Integer                                  ;
; pll_dsm_out_sel                      ; 1st_order              ; String                                          ;
; mimic_fbclk_type                     ; gclk                   ; String                                          ;
; pll_fbclk_mux_1                      ; glb                    ; String                                          ;
; pll_fbclk_mux_2                      ; fb_1                   ; String                                          ;
; pll_m_cnt_in_src                     ; ph_mux_clk             ; String                                          ;
; pll_vcoph_div                        ; 1                      ; Signed Integer                                  ;
; refclk1_frequency                    ; 0 MHz                  ; String                                          ;
; pll_clkin_0_src                      ; clk_0                  ; String                                          ;
; pll_clkin_1_src                      ; clk_0                  ; String                                          ;
; pll_clk_loss_sw_en                   ; false                  ; String                                          ;
; pll_auto_clk_sw_en                   ; false                  ; String                                          ;
; pll_manu_clk_sw_en                   ; false                  ; String                                          ;
; pll_clk_sw_dly                       ; 0                      ; Signed Integer                                  ;
; pll_extclk_0_cnt_src                 ; pll_extclk_cnt_src_vss ; String                                          ;
; pll_extclk_1_cnt_src                 ; pll_extclk_cnt_src_vss ; String                                          ;
+--------------------------------------+------------------------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: USB_USB_Reader:C_USB ;
+-------------------+-------+---------------------------------------+
; Parameter Name    ; Value ; Type                                  ;
+-------------------+-------+---------------------------------------+
; x_uc_data_size    ; 32    ; Signed Integer                        ;
; x_uc_dma_size_w32 ; 11    ; Signed Integer                        ;
; x_uc_dma_nb_w32   ; 2048  ; Signed Integer                        ;
; x_fifo_tx_size    ; 12    ; Signed Integer                        ;
; x_reset_active    ; '0'   ; Enumerated                            ;
+-------------------+-------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+-----------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                              ;
+------------------------+--------------+-----------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                        ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                      ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                      ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                    ;
; WIDTH                  ; 1            ; Signed Integer                                                                    ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                           ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                           ;
; extend_oe_disable      ; OFF          ; Untyped                                                                           ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                           ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                           ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                           ;
+------------------------+--------------+-----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component ;
+-------------------------+-------------+---------------------------------------------------+
; Parameter Name          ; Value       ; Type                                              ;
+-------------------------+-------------+---------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                           ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                        ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                      ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                      ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                    ;
; LPM_WIDTH               ; 33          ; Signed Integer                                    ;
; LPM_NUMWORDS            ; 4096        ; Signed Integer                                    ;
; LPM_WIDTHU              ; 12          ; Signed Integer                                    ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                           ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                           ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                           ;
; USE_EAB                 ; ON          ; Untyped                                           ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                           ;
; ENABLE_ECC              ; FALSE       ; Untyped                                           ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                           ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                           ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                    ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                    ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                           ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                           ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                           ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                           ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                           ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                           ;
; CBXI_PARAMETER          ; dcfifo_qhm1 ; Untyped                                           ;
+-------------------------+-------------+---------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: HFRB_GPIO_RX_SM:C_GPIO_RX0 ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type                                           ;
+----------------+-------+------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                     ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------+
; dcfifo Parameter Settings by Entity Instance                              ;
+----------------------------+----------------------------------------------+
; Name                       ; Value                                        ;
+----------------------------+----------------------------------------------+
; Number of entity instances ; 1                                            ;
; Entity Instance            ; HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                   ;
;     -- LPM_WIDTH           ; 33                                           ;
;     -- LPM_NUMWORDS        ; 4096                                         ;
;     -- LPM_SHOWAHEAD       ; OFF                                          ;
;     -- USE_EAB             ; ON                                           ;
+----------------------------+----------------------------------------------+


+------------------------------------------------------------------------+
; Port Connectivity Checks: "USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK" ;
+----------+-------+----------+------------------------------------------+
; Port     ; Type  ; Severity ; Details                                  ;
+----------+-------+----------+------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                             ;
; datain_l ; Input ; Info     ; Stuck at VCC                             ;
+----------+-------+----------+------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "USB_USB_Reader:C_USB"                                                                     ;
+------------+--------+----------+-------------------------------------------------------------------------------------+
; Port       ; Type   ; Severity ; Details                                                                             ;
+------------+--------+----------+-------------------------------------------------------------------------------------+
; x_state_g  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_wr_cnt_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_zlp_rq_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------------+--------+----------+-------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "PLL_MAIN:C_PLL"                                                                         ;
+----------+--------+----------+-------------------------------------------------------------------------------------+
; Port     ; Type   ; Severity ; Details                                                                             ;
+----------+--------+----------+-------------------------------------------------------------------------------------+
; outclk_1 ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+----------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; arriav_ddio_out       ; 1                           ;
; arriav_ff             ; 235                         ;
;     CLR               ; 95                          ;
;     ENA               ; 36                          ;
;     ENA CLR           ; 3                           ;
;     ENA CLR SLD       ; 11                          ;
;     plain             ; 90                          ;
; arriav_io_obuf        ; 49                          ;
; arriav_lcell_comb     ; 125                         ;
;     arith             ; 11                          ;
;         1 data inputs ; 11                          ;
;     normal            ; 114                         ;
;         0 data inputs ; 2                           ;
;         1 data inputs ; 8                           ;
;         2 data inputs ; 16                          ;
;         3 data inputs ; 16                          ;
;         4 data inputs ; 17                          ;
;         5 data inputs ; 18                          ;
;         6 data inputs ; 37                          ;
; boundary_port         ; 204                         ;
; generic_pll           ; 1                           ;
; stratixv_ram_block    ; 33                          ;
;                       ;                             ;
; Max LUT depth         ; 5.00                        ;
; Average LUT depth     ; 1.72                        ;
+-----------------------+-----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:00     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition
    Info: Processing started: Tue Jun 23 15:32:18 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off HFRB_GPIO_TOP -c HFRB_GPIO_TOP
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/u_util/exp/u_size.vhd
    Info (12022): Found design unit 1: U_Size File: J:/vhdl_db/trunk/lib/u_util/exp/u_size.vhd Line: 10
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/u_util/exp/u_util.vhd
    Info (12022): Found design unit 1: u_util File: J:/vhdl_db/trunk/lib/u_util/exp/u_util.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/u_util/src/u_onepulse.vhd
    Info (12022): Found design unit 1: U_OnePulse-A_behavioral File: J:/vhdl_db/trunk/lib/u_util/src/u_onepulse.vhd Line: 26
    Info (12023): Found entity 1: U_OnePulse File: J:/vhdl_db/trunk/lib/u_util/src/u_onepulse.vhd Line: 11
Info (12021): Found 2 design units, including 0 entities, in source file /vhdl_db/trunk/lib/usb_usb/exp/usb_usb.vhd
    Info (12022): Found design unit 1: usb_usb File: J:/vhdl_db/trunk/lib/usb_usb/exp/USB_USB.vhd Line: 11
    Info (12022): Found design unit 2: usb_usb-body File: J:/vhdl_db/trunk/lib/usb_usb/exp/USB_USB.vhd Line: 245
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/usb_uc_pclk.vhd
    Info (12022): Found design unit 1: usb_uc_pclk-SYN File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 53
    Info (12023): Found entity 1: USB_UC_PCLK File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/usb_usb/src/usb_usb_reader.vhd
    Info (12022): Found design unit 1: USB_USB_Reader-Behavioral File: J:/vhdl_db/trunk/lib/usb_usb/src/USB_USB_Reader.vhd Line: 49
    Info (12023): Found entity 1: USB_USB_Reader File: J:/vhdl_db/trunk/lib/usb_usb/src/USB_USB_Reader.vhd Line: 11
Info (12021): Found 1 design units, including 0 entities, in source file src/hfrb_gpio_global_const.vhd
    Info (12022): Found design unit 1: HFRB_GPIO_GLOBAL_CONST File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_GLOBAL_CONST.vhd Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file src/pll_main.vhd
    Info (12022): Found design unit 1: PLL_MAIN-rtl File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/PLL_MAIN.vhd Line: 21
    Info (12023): Found entity 1: PLL_MAIN File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/PLL_MAIN.vhd Line: 11
Info (12021): Found 1 design units, including 1 entities, in source file src/pll_main/pll_main_0002.v
    Info (12023): Found entity 1: PLL_MAIN_0002 File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/PLL_MAIN/PLL_MAIN_0002.v Line: 2
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/projets/hfrb_herdfebreadoutboard/src/hfrb_gpio_rx_sm.vhd
    Info (12022): Found design unit 1: HFRB_GPIO_RX_SM-Behavioral File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/src/HFRB_GPIO_RX_SM.vhd Line: 36
    Info (12023): Found entity 1: HFRB_GPIO_RX_SM File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/src/HFRB_GPIO_RX_SM.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file src/hfrb_gpio_top.vhd
    Info (12022): Found design unit 1: HFRB_GPIO_TOP-Behavioral File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 203
    Info (12023): Found entity 1: HFRB_GPIO_TOP File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file src/hfrb_usb_fifo.vhd
    Info (12022): Found design unit 1: hfrb_usb_fifo-SYN File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_USB_FIFO.vhd Line: 58
    Info (12023): Found entity 1: HFRB_USB_FIFO File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_USB_FIFO.vhd Line: 42
Info (12127): Elaborating entity "HFRB_GPIO_TOP" for the top level hierarchy
Info (12128): Elaborating entity "PLL_MAIN" for hierarchy "PLL_MAIN:C_PLL" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 259
Info (12128): Elaborating entity "PLL_MAIN_0002" for hierarchy "PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/PLL_MAIN.vhd Line: 34
Info (12128): Elaborating entity "altera_pll" for hierarchy "PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/PLL_MAIN/PLL_MAIN_0002.v Line: 88
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus
Info (12130): Elaborated megafunction instantiation "PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/PLL_MAIN/PLL_MAIN_0002.v Line: 88
Info (12133): Instantiated megafunction "PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i" with the following parameter: File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/PLL_MAIN/PLL_MAIN_0002.v Line: 88
    Info (12134): Parameter "fractional_vco_multiplier" = "false"
    Info (12134): Parameter "reference_clock_frequency" = "40.0 MHz"
    Info (12134): Parameter "operation_mode" = "direct"
    Info (12134): Parameter "number_of_clocks" = "2"
    Info (12134): Parameter "output_clock_frequency0" = "40.000000 MHz"
    Info (12134): Parameter "phase_shift0" = "0 ps"
    Info (12134): Parameter "duty_cycle0" = "50"
    Info (12134): Parameter "output_clock_frequency1" = "32.000000 MHz"
    Info (12134): Parameter "phase_shift1" = "0 ps"
    Info (12134): Parameter "duty_cycle1" = "50"
    Info (12134): Parameter "output_clock_frequency2" = "0 MHz"
    Info (12134): Parameter "phase_shift2" = "0 ps"
    Info (12134): Parameter "duty_cycle2" = "50"
    Info (12134): Parameter "output_clock_frequency3" = "0 MHz"
    Info (12134): Parameter "phase_shift3" = "0 ps"
    Info (12134): Parameter "duty_cycle3" = "50"
    Info (12134): Parameter "output_clock_frequency4" = "0 MHz"
    Info (12134): Parameter "phase_shift4" = "0 ps"
    Info (12134): Parameter "duty_cycle4" = "50"
    Info (12134): Parameter "output_clock_frequency5" = "0 MHz"
    Info (12134): Parameter "phase_shift5" = "0 ps"
    Info (12134): Parameter "duty_cycle5" = "50"
    Info (12134): Parameter "output_clock_frequency6" = "0 MHz"
    Info (12134): Parameter "phase_shift6" = "0 ps"
    Info (12134): Parameter "duty_cycle6" = "50"
    Info (12134): Parameter "output_clock_frequency7" = "0 MHz"
    Info (12134): Parameter "phase_shift7" = "0 ps"
    Info (12134): Parameter "duty_cycle7" = "50"
    Info (12134): Parameter "output_clock_frequency8" = "0 MHz"
    Info (12134): Parameter "phase_shift8" = "0 ps"
    Info (12134): Parameter "duty_cycle8" = "50"
    Info (12134): Parameter "output_clock_frequency9" = "0 MHz"
    Info (12134): Parameter "phase_shift9" = "0 ps"
    Info (12134): Parameter "duty_cycle9" = "50"
    Info (12134): Parameter "output_clock_frequency10" = "0 MHz"
    Info (12134): Parameter "phase_shift10" = "0 ps"
    Info (12134): Parameter "duty_cycle10" = "50"
    Info (12134): Parameter "output_clock_frequency11" = "0 MHz"
    Info (12134): Parameter "phase_shift11" = "0 ps"
    Info (12134): Parameter "duty_cycle11" = "50"
    Info (12134): Parameter "output_clock_frequency12" = "0 MHz"
    Info (12134): Parameter "phase_shift12" = "0 ps"
    Info (12134): Parameter "duty_cycle12" = "50"
    Info (12134): Parameter "output_clock_frequency13" = "0 MHz"
    Info (12134): Parameter "phase_shift13" = "0 ps"
    Info (12134): Parameter "duty_cycle13" = "50"
    Info (12134): Parameter "output_clock_frequency14" = "0 MHz"
    Info (12134): Parameter "phase_shift14" = "0 ps"
    Info (12134): Parameter "duty_cycle14" = "50"
    Info (12134): Parameter "output_clock_frequency15" = "0 MHz"
    Info (12134): Parameter "phase_shift15" = "0 ps"
    Info (12134): Parameter "duty_cycle15" = "50"
    Info (12134): Parameter "output_clock_frequency16" = "0 MHz"
    Info (12134): Parameter "phase_shift16" = "0 ps"
    Info (12134): Parameter "duty_cycle16" = "50"
    Info (12134): Parameter "output_clock_frequency17" = "0 MHz"
    Info (12134): Parameter "phase_shift17" = "0 ps"
    Info (12134): Parameter "duty_cycle17" = "50"
    Info (12134): Parameter "pll_type" = "General"
    Info (12134): Parameter "pll_subtype" = "General"
Info (12128): Elaborating entity "USB_USB_Reader" for hierarchy "USB_USB_Reader:C_USB" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 270
Info (12128): Elaborating entity "USB_UC_PCLK" for hierarchy "USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK" File: J:/vhdl_db/trunk/lib/usb_usb/src/USB_USB_Reader.vhd Line: 87
Info (12128): Elaborating entity "altddio_out" for hierarchy "USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component" File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 60
Info (12130): Elaborated megafunction instantiation "USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component" File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 60
Info (12133): Instantiated megafunction "USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component" with the following parameter: File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 60
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "extend_oe_disable" = "OFF"
    Info (12134): Parameter "invert_output" = "OFF"
    Info (12134): Parameter "oe_reg" = "UNREGISTERED"
    Info (12134): Parameter "power_up_high" = "OFF"
    Info (12134): Parameter "width" = "1"
    Info (12134): Parameter "lpm_hint" = "UNUSED"
    Info (12134): Parameter "lpm_type" = "altddio_out"
Info (12021): Found 1 design units, including 1 entities, in source file db/ddio_out_b2j.tdf
    Info (12023): Found entity 1: ddio_out_b2j File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/ddio_out_b2j.tdf Line: 27
Info (12128): Elaborating entity "ddio_out_b2j" for hierarchy "USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altddio_out.tdf Line: 100
Info (12128): Elaborating entity "HFRB_USB_FIFO" for hierarchy "HFRB_USB_FIFO:C_FIFO" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 308
Info (12128): Elaborating entity "dcfifo" for hierarchy "HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_USB_FIFO.vhd Line: 100
Info (12130): Elaborated megafunction instantiation "HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_USB_FIFO.vhd Line: 100
Info (12133): Instantiated megafunction "HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component" with the following parameter: File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_USB_FIFO.vhd Line: 100
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "4096"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "33"
    Info (12134): Parameter "lpm_widthu" = "12"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_qhm1.tdf
    Info (12023): Found entity 1: dcfifo_qhm1 File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dcfifo_qhm1.tdf Line: 40
Info (12128): Elaborating entity "dcfifo_qhm1" for hierarchy "HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf Line: 190
Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_rab.tdf
    Info (12023): Found entity 1: a_gray2bin_rab File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/a_gray2bin_rab.tdf Line: 22
Info (12128): Elaborating entity "a_gray2bin_rab" for hierarchy "HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|a_gray2bin_rab:rdptr_g_gray2bin" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dcfifo_qhm1.tdf Line: 53
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_oh6.tdf
    Info (12023): Found entity 1: a_graycounter_oh6 File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/a_graycounter_oh6.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_oh6" for hierarchy "HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|a_graycounter_oh6:rdptr_g1p" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dcfifo_qhm1.tdf Line: 55
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_kvb.tdf
    Info (12023): Found entity 1: a_graycounter_kvb File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/a_graycounter_kvb.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_kvb" for hierarchy "HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|a_graycounter_kvb:wrptr_g1p" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dcfifo_qhm1.tdf Line: 56
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_6la1.tdf
    Info (12023): Found entity 1: altsyncram_6la1 File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/altsyncram_6la1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_6la1" for hierarchy "HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|altsyncram_6la1:fifo_ram" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dcfifo_qhm1.tdf Line: 57
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_c09.tdf
    Info (12023): Found entity 1: dffpipe_c09 File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dffpipe_c09.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_c09" for hierarchy "HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|dffpipe_c09:rs_brp" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dcfifo_qhm1.tdf Line: 64
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_sal.tdf
    Info (12023): Found entity 1: alt_synch_pipe_sal File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/alt_synch_pipe_sal.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_sal" for hierarchy "HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dcfifo_qhm1.tdf Line: 66
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_d09.tdf
    Info (12023): Found entity 1: dffpipe_d09 File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dffpipe_d09.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_d09" for hierarchy "HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_sal:rs_dgwp|dffpipe_d09:dffpipe13" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/alt_synch_pipe_sal.tdf Line: 33
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_tal.tdf
    Info (12023): Found entity 1: alt_synch_pipe_tal File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/alt_synch_pipe_tal.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_tal" for hierarchy "HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dcfifo_qhm1.tdf Line: 67
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_e09.tdf
    Info (12023): Found entity 1: dffpipe_e09 File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dffpipe_e09.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_e09" for hierarchy "HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|alt_synch_pipe_tal:ws_dgrp|dffpipe_e09:dffpipe16" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/alt_synch_pipe_tal.tdf Line: 33
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_c06.tdf
    Info (12023): Found entity 1: cmpr_c06 File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/cmpr_c06.tdf Line: 22
Info (12128): Elaborating entity "cmpr_c06" for hierarchy "HFRB_USB_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_qhm1:auto_generated|cmpr_c06:rdempty_eq_comp" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/db/dcfifo_qhm1.tdf Line: 71
Info (12128): Elaborating entity "HFRB_GPIO_RX_SM" for hierarchy "HFRB_GPIO_RX_SM:C_GPIO_RX0" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 326
Warning (14284): Synthesized away the following node(s):
    Warning (14285): Synthesized away the following PLL node(s):
        Warning (14320): Synthesized away node "PLL_MAIN:C_PLL|PLL_MAIN_0002:pll_main_inst|altera_pll:altera_pll_i|outclk_wire[1]" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v Line: 748
Warning (13034): The following nodes have both tri-state and non-tri-state drivers
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[0]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[1]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[2]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[3]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[4]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[5]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[6]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[7]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[8]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[9]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[10]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[11]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[12]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[13]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[14]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[15]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[16]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[17]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[18]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[19]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[20]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[21]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[22]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[23]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[24]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[25]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[26]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[27]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[28]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[29]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[30]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[31]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
Warning (13032): The following tri-state nodes are fed by constants
    Warning (13033): The pin "x_IO_8A[0]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[1]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[2]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[3]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[4]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[5]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[6]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[7]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[8]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[9]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[10]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[11]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[12]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[13]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[14]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
    Warning (13033): The pin "x_IO_8A[15]" is fed by GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 49
Warning (13009): TRI or OPNDRN buffers permanently enabled
    Warning (13010): Node "x_UC_DQ[0]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[1]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[2]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[3]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[4]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[5]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[6]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[7]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[8]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[9]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[10]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[11]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[12]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[13]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[14]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[15]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[16]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[17]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[18]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[19]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[20]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[21]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[22]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[23]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[24]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[25]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[26]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[27]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[28]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[29]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[30]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
    Warning (13010): Node "x_UC_DQ[31]~synth" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 25
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "x_UC_SLRDn" is stuck at VCC File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 29
    Warning (13410): Pin "x_UC_SLOEn" is stuck at VCC File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 30
    Warning (13410): Pin "x_UC_A[0]" is stuck at GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 32
    Warning (13410): Pin "x_UC_A[1]" is stuck at GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 32
    Warning (13410): Pin "x_UC_UART_CTSn" is stuck at VCC File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 40
    Warning (13410): Pin "x_DAC_CS" is stuck at GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 44
    Warning (13410): Pin "x_DAC_SDI" is stuck at GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 45
    Warning (13410): Pin "x_DAC_SCK" is stuck at GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 46
    Warning (13410): Pin "x_4A_TXN41" is stuck at VCC File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 77
    Warning (13410): Pin "x_4A_TXN44" is stuck at GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 79
    Warning (13410): Pin "x_4A_TXN53" is stuck at VCC File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 87
    Warning (13410): Pin "x_3A_TXP6" is stuck at GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 114
    Warning (13410): Pin "x_3A_RXP5" is stuck at GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 115
    Warning (13410): Pin "x_3A_TXN8" is stuck at GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 116
    Warning (13410): Pin "x_3A_RXN7" is stuck at GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 117
    Warning (13410): Pin "x_3A_TXP8" is stuck at GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 118
    Warning (13410): Pin "x_3A_RXP7" is stuck at GND File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 119
Info (286030): Timing-Driven Synthesis is running
Info (17016): Found the following redundant logic cells in design
    Info (17048): Logic cell "sl_int_usb_ready" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 224
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 10 node(s), including 1 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 103 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "x_UC_FLAGS[1]" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 33
    Warning (15610): No output dependent on input pin "x_UC_FLAGS[2]" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 33
    Warning (15610): No output dependent on input pin "x_UC_FLAGS[3]" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 33
    Warning (15610): No output dependent on input pin "x_UC_UART_RTSn" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 39
    Warning (15610): No output dependent on input pin "x_3B_RX31" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 52
    Warning (15610): No output dependent on input pin "x_3B_RX26" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 55
    Warning (15610): No output dependent on input pin "x_3B_TXN25" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 58
    Warning (15610): No output dependent on input pin "x_3B_TXP25" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 59
    Warning (15610): No output dependent on input pin "x_3B_RXP27" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 60
    Warning (15610): No output dependent on input pin "x_3B_RXN27" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 61
    Warning (15610): No output dependent on input pin "x_3B_TXP29" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 64
    Warning (15610): No output dependent on input pin "x_3B_TXN29" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 65
    Warning (15610): No output dependent on input pin "x_3B_TXP32" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 66
    Warning (15610): No output dependent on input pin "x_3B_TXN32" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 67
    Warning (15610): No output dependent on input pin "x_3B_TXP33" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 68
    Warning (15610): No output dependent on input pin "x_3B_TXN33" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 69
    Warning (15610): No output dependent on input pin "x_3B_RXP35" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 70
    Warning (15610): No output dependent on input pin "x_3B_RXN35" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 71
    Warning (15610): No output dependent on input pin "x_3B_RXP38" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 72
    Warning (15610): No output dependent on input pin "x_3B_RXN38" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 73
    Warning (15610): No output dependent on input pin "x_3B_TXP40" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 74
    Warning (15610): No output dependent on input pin "x_3B_TXN40" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 75
    Warning (15610): No output dependent on input pin "x_4A_TXP45" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 80
    Warning (15610): No output dependent on input pin "x_4A_TXN45" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 81
    Warning (15610): No output dependent on input pin "x_4A_TXN52" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 85
    Warning (15610): No output dependent on input pin "x_4A_TXP56" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 88
    Warning (15610): No output dependent on input pin "x_4A_TXN56" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 89
    Warning (15610): No output dependent on input pin "x_4A_TXP57" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 90
    Warning (15610): No output dependent on input pin "x_4A_TXN57" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 91
    Warning (15610): No output dependent on input pin "x_4A_TXP60" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 94
    Warning (15610): No output dependent on input pin "x_4A_TXN60" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 95
    Warning (15610): No output dependent on input pin "x_4A_TXP61" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 96
    Warning (15610): No output dependent on input pin "x_4A_TXN61" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 97
    Warning (15610): No output dependent on input pin "x_4A_RXP62" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 98
    Warning (15610): No output dependent on input pin "x_4A_RXN62" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 99
    Warning (15610): No output dependent on input pin "x_4A_TXP64" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 100
    Warning (15610): No output dependent on input pin "x_4A_TXN64" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 101
    Warning (15610): No output dependent on input pin "x_5A_TXP1" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 122
    Warning (15610): No output dependent on input pin "x_5A_TXN1" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 123
    Warning (15610): No output dependent on input pin "x_5A_RXP6" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 124
    Warning (15610): No output dependent on input pin "x_5A_RXN6" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 125
    Warning (15610): No output dependent on input pin "x_5A_RXP8" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 126
    Warning (15610): No output dependent on input pin "x_5A_RXN8" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 127
    Warning (15610): No output dependent on input pin "x_5A_RXP4" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 128
    Warning (15610): No output dependent on input pin "x_5A_RXN4" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 129
    Warning (15610): No output dependent on input pin "x_5A_TXP7" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 130
    Warning (15610): No output dependent on input pin "x_5A_TXN7" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 131
    Warning (15610): No output dependent on input pin "x_5A_RXN2" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 132
    Warning (15610): No output dependent on input pin "x_7A_RXN1" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 135
    Warning (15610): No output dependent on input pin "x_7A_RXP1" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 136
    Warning (15610): No output dependent on input pin "x_7A_RXP5" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 137
    Warning (15610): No output dependent on input pin "x_7A_RXN5" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 138
    Warning (15610): No output dependent on input pin "x_7A_TXP8" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 139
    Warning (15610): No output dependent on input pin "x_7A_TXN8" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 140
    Warning (15610): No output dependent on input pin "x_7A_RXP9" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 141
    Warning (15610): No output dependent on input pin "x_7A_RXN9" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 142
    Warning (15610): No output dependent on input pin "x_7A_TXP2" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 144
    Warning (15610): No output dependent on input pin "x_7A_TXN2" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 145
    Warning (15610): No output dependent on input pin "x_7A_RXP3" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 146
    Warning (15610): No output dependent on input pin "x_7A_RXN3" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 147
    Warning (15610): No output dependent on input pin "x_7A_TXP4" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 148
    Warning (15610): No output dependent on input pin "x_7A_TXN4" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 149
    Warning (15610): No output dependent on input pin "x_7A_TXP6" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 150
    Warning (15610): No output dependent on input pin "x_7A_TXN6" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 151
    Warning (15610): No output dependent on input pin "x_7A_RXP7" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 152
    Warning (15610): No output dependent on input pin "x_7A_RXN7" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 153
    Warning (15610): No output dependent on input pin "x_7A_TXP10" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 154
    Warning (15610): No output dependent on input pin "x_7A_TXN10" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 155
    Warning (15610): No output dependent on input pin "x_7A_RXP11" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 156
    Warning (15610): No output dependent on input pin "x_7A_RXN11" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 157
    Warning (15610): No output dependent on input pin "x_7A_TXP12" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 158
    Warning (15610): No output dependent on input pin "x_7A_TXN12" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 159
    Warning (15610): No output dependent on input pin "x_7A_RXP13" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 161
    Warning (15610): No output dependent on input pin "x_7A_RXN13" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 162
    Warning (15610): No output dependent on input pin "x_7A_TXP14" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 163
    Warning (15610): No output dependent on input pin "x_7A_TXN14" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 164
    Warning (15610): No output dependent on input pin "x_7A_RXP15" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 165
    Warning (15610): No output dependent on input pin "x_7A_RXN15" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 166
    Warning (15610): No output dependent on input pin "x_7A_TXP16" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 167
    Warning (15610): No output dependent on input pin "x_7A_TXN16" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 168
    Warning (15610): No output dependent on input pin "x_7A_RXP37" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 169
    Warning (15610): No output dependent on input pin "x_7A_RXN37" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 170
    Warning (15610): No output dependent on input pin "x_7A_RXP33" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 171
    Warning (15610): No output dependent on input pin "x_7A_RXN33" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 172
    Warning (15610): No output dependent on input pin "x_8A_TXP50" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 175
    Warning (15610): No output dependent on input pin "x_8A_TXN50" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 176
    Warning (15610): No output dependent on input pin "x_8A_TXP52" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 177
    Warning (15610): No output dependent on input pin "x_8A_TXN52" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 178
    Warning (15610): No output dependent on input pin "x_8A_TXP54" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 179
    Warning (15610): No output dependent on input pin "x_8A_TXN54" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 180
    Warning (15610): No output dependent on input pin "x_8A_TXP56" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 181
    Warning (15610): No output dependent on input pin "x_8A_RXP51" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 182
    Warning (15610): No output dependent on input pin "x_8A_RXN51" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 183
    Warning (15610): No output dependent on input pin "x_8A_RXP53" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 184
    Warning (15610): No output dependent on input pin "x_8A_RXN53" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 185
    Warning (15610): No output dependent on input pin "x_8A_RXP55" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 186
    Warning (15610): No output dependent on input pin "x_8A_RXN55" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 187
    Warning (15610): No output dependent on input pin "x_8A_TXN56" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 188
    Warning (15610): No output dependent on input pin "x_BOARDID[0]" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 191
    Warning (15610): No output dependent on input pin "x_BOARDID[1]" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 191
    Warning (15610): No output dependent on input pin "x_BOARDID[2]" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 191
    Warning (15610): No output dependent on input pin "x_BOARDID[3]" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 191
    Warning (15610): No output dependent on input pin "x_NIM_IN[1]" File: J:/vhdl_db/trunk/projets/HFRB_HerdFEBReadoutBoard/etc/GPIO/src/HFRB_GPIO_TOP.vhd Line: 193
Info (21057): Implemented 524 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 114 input pins
    Info (21059): Implemented 41 output pins
    Info (21060): Implemented 49 bidirectional pins
    Info (21061): Implemented 285 logic cells
    Info (21064): Implemented 33 RAM segments
    Info (21065): Implemented 1 PLLs
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 209 warnings
    Info: Peak virtual memory: 4902 megabytes
    Info: Processing ended: Tue Jun 23 15:32:34 2020
    Info: Elapsed time: 00:00:16
    Info: Total CPU time (on all processors): 00:00:26


