SER/DES

The SER/DES IP Core is able to implement multi-channel SERialization, DESerialization and SER/DES applications.

The IP Core instantiates the required number NX_SER and NX_DES of a same SER_DES group. It also provides DESerializers automatic adjustments (data/clock and word alignment – also called calibration process) for high speed safe communications.

For SERializers, the IP Core also includes a mechanism that allows to send a user’s defined training value to external receivers.

In addition, the IP Core generates automatically all internal clocks by using a Clock Generator (CKG), taking as reference the incoming word clock. Two of those clocks (SCK – word clock and DCK – auxiliary calibration clock) are distributed by the low skew network and can be used for other portions of the user’s design.

The IP Core can manage simultaneously SERializers and DESerializers in a same group – while they share some common parameters, such as:

• All SER and all DES must be located in a single complex IO bank. (banks 2, 3, 4, 5, 9, 10, 11 or 12).
• All SER and DES of a same group (same bank) must use an electrical standard compatible with the VCCIO of the bank.
• All SER and DES of a same group must share the same bit rate and word rate, and then the same serialization/deserialization factor.

The maximum total number of SER and DES elements in a same group is 30 (no differential mode and serialization/deserialization factor from 3 to 5), or 15 in differential mode or serialization/deserialization factor from 3 to 10.

In a same NG-MEDIUM design, up to 4 SER/DES groups can be implemented.