Systolic

The NX_SYSTOLIC_FIR is part of the NanoXplore DSP IP Cores. It implements a fully programmable parallel N-TAP FIR filter. It supports up to 56 taps, and supports the highest working frequency.

It was developed to take full advantage of the NG-MEDIUM DSP blocks architecture and direct routing chaining features.

All filter parameters are be user’s defined. No need to understand about architecture details to get the maximum performance.

The implementation of the NX_SYSTOLIC_FIR requires 1 DSP block per tap. No additional logic is required.

The next figure shows the NX_SYSTOLIC_FIR inputs and outputs.

The following is a summary of the features:

• Fully user’s programmable parallel FIR filter (highest performance)
• Single clock (fully synchronous)
• Optional Synchronous reset (SRST - can be tied to ‘0’ if not used)
• Optional enable to activate of freeze all internal registers (ENA – can be tied to ‘1’ if not used)
• Up to 56 taps
• Data width: Up to 18-bit
• Coefficient width: Up to 24-bit
• Dynamic or fixed coefficients