Cobham Gaisler AB
FTAHBRAM
FTAHBRAM implements on-chip RAM with added Error Detection And Correction (EDAC). The memory is accessed through an AHB slave interface. Memory size is configurable in binary steps through a VHDL generic. Minimum size is 1KiB and maximum size is dependent on target technology and physical resources.
The on-chip memory implements volatile memory that is protected by means of Error Detection And Correction (EDAC). One error can be corrected and two errors can be detected, which is performed by using a (32, 7) BCH code or by technology specific protection provided by the target technology RAMs (implementation option, if supported by target technology). Some of the optional features available are single error counter, diagnostic reads and writes and additional pipeline registers. Configuration is performed via a configuration register.
The estimated resource utilization of the FTAHBRAM is:
The next figure shows the FTAHBRAM interfaces.
The following is a summary of the features:
- Configurable memory size
- EDAC protection with single error correction and double error detection
- Read and write diagnostics
- Error counter