Cobham Gaisler AB
FTMCTRL
The FTMCTRL can handle four types of devices: PROM, asynchronous static RAM (SRAM), synchronous dynamic RAM (SDRAM) and memory mapped I/O devices (I/O). The PROM, SRAM and SDRAM areas can be EDAC-protected using a (39, 7) BCH code, providing single error correction and double-error detection for each 32-bit memory word. The SDRAM area can optionally also be protected using Reed-Solomon coding. In this case a 16-bit checksum is used for each 32-bit word, and any two adjacent 4-bit (nibble) errors can be corrected.
The core supports 8-/16- and 32-bit wide PROM, IO and SRAM memories/devices. The SDRAM can either be on the same memory bus as the other memories or on a separate bus. 32-bit wide memories are supported in the former case while the latter supports both 32/64-bits.
External chip-selects are provided for up to to four PROM banks, one I/O bank, five SRAM banks and two SDRAM banks.
Memory accesses are performed through an AHB slave interface while configuration registers are accessed through an APB interface.
The estimated resource utilization of the FTMCTRL is:
The following is a summary of the features:
- Combined PROM/IO/SRAM/SDRAM memory controller with EDAC
- Support for 8-, 16- and 32-bit PROM, SRAM and IO area
- Support for PC100/PC133 compatible SDRAMs
- Up to 4 PROM banks
- Up to 5 SRAM banks
- Up to 2 SDRAM banks
- One IO bank
- Programmable wait states
- Support for optional bus ready signaling from PROM, SRAM and IO areas
- Support for optional access error signaling from PROM, SRAM and IO areas