Cobham Gaisler AB
GRPCI2
The GRPCI2 core is a bridge between the PCI bus and the AMBA AHB bus. The core is capable of connecting to the PCI bus via both a target and a initiator/master interface. The connection to the AMBA bus is an AHB master interface for the PCI target functionality and an AHB slave interface for the PCI initiator functionality. The core also contains a DMA controller. For the DMA functionality, the core uses the PCI initiator to connect to the PCI bus and an AHB master to connect to the AMBA bus. Configuration registers in the core are accessible via a AMBA APB slave interface or extended configuration space.
The PCI interface is compatible with the 2.3 PCI Local Bus Specification.
The estimated resource utilization of the GRPCI2 is:
The following is a summary of the features:
- 32-bit PCI interface
- Configurable as PCI master and target
- AMBA AHB/APB 2.0 back end interface
- Configurable FIFOs for both master and target operation
- Supports incremental bursts and single accesses
- Optional DMA engine add on
- Autonomous data transfer using descriptor controlled DMA
- Memory read, memory write
- Memory read multiple
- I/O read, I/O write
- Type 0 and 1 configuration read and write
- Host bridging
- Type 0 configuration space header
- Configuration read and write
- Parity generation (PAR)
- Configurable number of BARs
- Memory read, memory write
- Memory read multiple
- Memory read line
- Memory write and invalidate
Bus Master capabilities
Target capabilities