Cobham Gaisler AB
SPICTRL
The core provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus and can be dynamically configured to function either as a SPI master or a slave. The SPI bus parameters are highly configurable via registers. Core features also include configurable word length, bit ordering, clock gap insertion, automatic slave select and automatic periodic transfers of a specified length. All SPI modes are supported and optionally also dual SPI, quad SPI, and a 3-wire protocol where one bidirectional data line is used. In slave mode the core synchronizes the incoming clock and can operate in systems where other SPI devices are driven by asynchronous clocks.
The estimated resource utilization of the SPICTRL is:
The next figure shows the SPICTRL interfaces.
The following is a summary of the features:
- Support for all SPI modes
- Optional support for dual SPI, quad SPI and 3-wire protocol
- Configurable word length
- Configurable bit ordering
- Clock gap insertion
- Automatic slave select
- Automatic periodic transfers