Analysis & Synthesis report for FEE_Control
Wed Jun 18 10:51:35 2025
Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis IP Cores Summary
 10. State Machine - |FEE_Control|s_state
 11. State Machine - |FEE_Control|fee_controller:C_FEECONTROLLER|s_tx_state
 12. State Machine - |FEE_Control|fee_controller:C_FEECONTROLLER|s_rx_state
 13. State Machine - |FEE_Control|USER_GET_CONFIG_RANGE_RD:C_PEDESTALS_USER_GET|sl_int_state
 14. State Machine - |FEE_Control|USER_GET_CONFIG_RANGE_RD:C_HOUSEKEEPING_USER_GET|sl_int_state
 15. State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|sl_int_state
 16. State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER|sl_int_state
 17. State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_timeout_state
 18. State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_process_state
 19. State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state
 20. State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_timeout_state
 21. State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state
 22. State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_state
 23. State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_state
 24. State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_start_state
 25. Registers Protected by Synthesis
 26. Registers Removed During Synthesis
 27. Removed Registers Triggering Further Register Optimizations
 28. General Register Statistics
 29. Inverted Register Statistics
 30. Multiplexer Restructuring Statistics (Restructuring Performed)
 31. Source assignments for Top-level Entity: |FEE_Control
 32. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component
 33. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated
 34. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component
 35. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated
 36. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_bg6:rdptr_g1p
 37. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_7ub:wrptr_g1p
 38. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|altsyncram_cia1:fifo_ram
 39. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:rs_brp
 40. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:rs_bwp
 41. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp
 42. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13
 43. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_brp
 44. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_bwp
 45. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp
 46. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16
 47. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated
 48. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_cu6:rdptr_g1p
 49. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_9cc:wrptr_g1p
 50. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|altsyncram_po91:fifo_ram
 51. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp
 52. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12
 53. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_brp
 54. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_bwp
 55. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp
 56. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16
 57. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|cntr_osd:cntr_b
 58. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated
 59. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_du6:rdptr_g1p
 60. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_8cc:wrptr_g1p
 61. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|altsyncram_qo91:fifo_ram
 62. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp
 63. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12
 64. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp
 65. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15
 66. Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|cntr_osd:cntr_b
 67. Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component
 68. Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated
 69. Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|a_graycounter_ov6:rdptr_g1p
 70. Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|a_graycounter_kdc:wrptr_g1p
 71. Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|altsyncram_m8d1:fifo_ram
 72. Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|dffpipe_pe9:rs_brp
 73. Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|dffpipe_pe9:rs_bwp
 74. Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp
 75. Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13
 76. Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|dffpipe_pe9:ws_brp
 77. Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|dffpipe_pe9:ws_bwp
 78. Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp
 79. Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16
 80. Source assignments for UGB_CFG_DPRAM:C_DPRAM|altsyncram:altsyncram_component|altsyncram_s1v3:auto_generated
 81. Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component
 82. Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated
 83. Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|a_graycounter_ov6:rdptr_g1p
 84. Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|a_graycounter_kdc:wrptr_g1p
 85. Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|altsyncram_s5d1:fifo_ram
 86. Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp
 87. Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6
 88. Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp
 89. Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9
 90. Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component
 91. Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated
 92. Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|a_graycounter_bu6:rdptr_g1p
 93. Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|a_graycounter_7cc:wrptr_g1p
 94. Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|altsyncram_03d1:fifo_ram
 95. Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp
 96. Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe10
 97. Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp
 98. Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_jd9:dffpipe13
 99. Source assignments for L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo|altsyncram_j0i1:FIFOram
100. Parameter Settings for User Entity Instance: PLL_60:C_PLL|PLL_60_0002:pll_60_inst|altera_pll:altera_pll_i
101. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB
102. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB
103. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component
104. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component
105. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC
106. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC
107. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER
108. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER
109. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART
110. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1
111. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART
112. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_bdgen:\g_dbgen:C_BDGEN
113. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER
114. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER
115. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component
116. Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component
117. Parameter Settings for User Entity Instance: UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component
118. Parameter Settings for User Entity Instance: UGB_CFG_DPRAM:C_DPRAM|altsyncram:altsyncram_component
119. Parameter Settings for User Entity Instance: USER_GET_CONFIG_RANGE_RD:C_HOUSEKEEPING_USER_GET
120. Parameter Settings for User Entity Instance: USER_GET_CONFIG_RANGE_RD:C_PEDESTALS_USER_GET
121. Parameter Settings for User Entity Instance: UFP_USER_SETGET_ACK:C_GET_ACK
122. Parameter Settings for User Entity Instance: SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component
123. Parameter Settings for User Entity Instance: SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component
124. Parameter Settings for User Entity Instance: L0_FIFO:C_L0_FIFO|scfifo:scfifo_component
125. dcfifo Parameter Settings by Entity Instance
126. scfifo Parameter Settings by Entity Instance
127. altsyncram Parameter Settings by Entity Instance
128. Port Connectivity Checks: "fee_controller:C_FEECONTROLLER"
129. Port Connectivity Checks: "serdes:SERDES|GCLK:RxClk_Buf|GCLK_altclkctrl_0:altclkctrl_0|GCLK_altclkctrl_0_sub:GCLK_altclkctrl_0_sub_component"
130. Port Connectivity Checks: "USER_GET_CONFIG_RANGE_RD:C_HOUSEKEEPING_USER_GET"
131. Port Connectivity Checks: "UGB_DATA_FIFO:C_FIFO"
132. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER"
133. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER"
134. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_bdgen:\g_dbgen:C_BDGEN"
135. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART"
136. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER"
137. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC"
138. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK"
139. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB"
140. Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB"
141. Post-Synthesis Netlist Statistics for Top Partition
142. Elapsed Time Per Partition
143. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
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functions, and any output files from any of the foregoing 
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details.



+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                      ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status     ; Successful - Wed Jun 18 10:51:35 2025           ;
; Quartus Prime Version           ; 18.0.0 Build 614 04/24/2018 SJ Standard Edition ;
; Revision Name                   ; FEE_Control                                     ;
; Top-level Entity Name           ; FEE_Control                                     ;
; Family                          ; Cyclone V                                       ;
; Logic utilization (in ALMs)     ; N/A                                             ;
; Total registers                 ; 5319                                            ;
; Total pins                      ; 207                                             ;
; Total virtual pins              ; 0                                               ;
; Total block memory bits         ; 67,776                                          ;
; Total DSP Blocks                ; 0                                               ;
; Total HSSI RX PCSs              ; 0                                               ;
; Total HSSI PMA RX Deserializers ; 0                                               ;
; Total HSSI TX PCSs              ; 0                                               ;
; Total HSSI PMA TX Serializers   ; 0                                               ;
; Total PLLs                      ; 1                                               ;
; Total DLLs                      ; 0                                               ;
+---------------------------------+-------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                             ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                          ; Setting            ; Default Value      ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                          ; 5CEBA7F23C8        ;                    ;
; Top-level entity name                                                           ; FEE_Control        ; FEE_Control        ;
; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
; Maximum processors allowed for parallel compilation                             ; 4                  ;                    ;
; VHDL Show LMF Mapping Messages                                                  ; Off                ;                    ;
; VHDL Version                                                                    ; VHDL_2008          ; VHDL_1993          ;
; Use smart compilation                                                           ; Off                ; Off                ;
; Enable parallel Assembler and Timing Analyzer during compilation                ; On                 ; On                 ;
; Enable compact report table                                                     ; Off                ; Off                ;
; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
; Preserve fewer node names                                                       ; On                 ; On                 ;
; Intel FPGA IP Evaluation Mode                                                   ; Enable             ; Enable             ;
; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
; State Machine Processing                                                        ; Auto               ; Auto               ;
; Safe State Machine                                                              ; Off                ; Off                ;
; Extract Verilog State Machines                                                  ; On                 ; On                 ;
; Extract VHDL State Machines                                                     ; On                 ; On                 ;
; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
; Parallel Synthesis                                                              ; On                 ; On                 ;
; DSP Block Balancing                                                             ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                              ; On                 ; On                 ;
; Power-Up Don't Care                                                             ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
; Remove Duplicate Registers                                                      ; On                 ; On                 ;
; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
; Optimization Technique                                                          ; Balanced           ; Balanced           ;
; Carry Chain Length                                                              ; 70                 ; 70                 ;
; Auto Carry Chains                                                               ; On                 ; On                 ;
; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
; Auto ROM Replacement                                                            ; On                 ; On                 ;
; Auto RAM Replacement                                                            ; On                 ; On                 ;
; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
; Strict RAM Replacement                                                          ; Off                ; Off                ;
; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                           ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
; Report Parameter Settings                                                       ; On                 ; On                 ;
; Report Source Assignments                                                       ; On                 ; On                 ;
; Report Connectivity Checks                                                      ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
; Power Optimization During Synthesis                                             ; Normal compilation ; Normal compilation ;
; HDL message level                                                               ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                            ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
; Block Design Naming                                                             ; Auto               ; Auto               ;
; SDC constraint protection                                                       ; Off                ; Off                ;
; Synthesis Effort                                                                ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
+---------------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 16          ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   0.0%      ;
;     Processor 3            ;   0.0%      ;
;     Processor 4            ;   0.0%      ;
+----------------------------+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                                                          ;
+------------------------------------------------------------------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path                                                         ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                              ; Library ;
+------------------------------------------------------------------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------------+---------+
; src/serial_communication/decoder_4b5b.vhd                                                ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/decoder_4b5b.vhd  ;         ;
; src/serial_communication/4b5b_encoder.vhd                                                ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/4b5b_encoder.vhd  ;         ;
; src/serial_communication/Serializer.vhd                                                  ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/Serializer.vhd    ;         ;
; src/serial_communication/Serdes.vhd                                                      ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/Serdes.vhd        ;         ;
; src/serial_communication/Deserializer.vhd                                                ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/Deserializer.vhd  ;         ;
; ../../../lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd               ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd        ;         ;
; ../../../lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd               ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd        ;         ;
; src/fee_controller/fee_controller.vhd                                                    ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/fee_controller/fee_controller.vhd      ;         ;
; src/FEE_Control.vhd                                                                      ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd                        ;         ;
; ../../../lib/u_util/exp/u_size.vhd                                                       ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/u_util/exp/u_size.vhd                                                ;         ;
; ../../../lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd                                   ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd                            ;         ;
; ../../../lib/usb_usb/exp/USB_USB.vhd                                                     ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/usb_usb/exp/USB_USB.vhd                                              ;         ;
; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                                      ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                               ;         ;
; ../../../lib/usb_usb/src/USB_USB_Reader.vhd                                              ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/usb_usb/src/USB_USB_Reader.vhd                                       ;         ;
; ../../../lib/ser_serialCommunication/exp/ser_serialCommunication.vhd                     ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/exp/ser_serialCommunication.vhd              ;         ;
; ../../../lib/ser_serialCommunication/exp/ser_crc_pck.vhd                                 ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/exp/ser_crc_pck.vhd                          ;         ;
; ../../../lib/ser_serialCommunication/src/ser_crc_pck_polynomial.vhd                      ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc_pck_polynomial.vhd               ;         ;
; ../../../lib/ser_serialCommunication/src/ser_crc.vhd                                     ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc.vhd                              ;         ;
; ../../../lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd        ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd ;         ;
; ../../../lib/ser_serialCommunication/src/ser_uart_ser.vhd                                ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_ser.vhd                         ;         ;
; ../../../lib/ser_serialCommunication/src/ser_uart_deser.vhd                              ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_deser.vhd                       ;         ;
; ../../../lib/ser_serialCommunication/src/ser_data_5_bits_filter.vhd                      ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_data_5_bits_filter.vhd               ;         ;
; ../../../lib/ser_serialCommunication/src/ser_uart_bdgen.vhd                              ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_bdgen.vhd                       ;         ;
; ../../../lib/ser_serialCommunication/src/ser_uart.vhd                                    ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart.vhd                             ;         ;
; ../../../lib/ser_serialCommunication/src/ser_uart_wrapper.vhd                            ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper.vhd                     ;         ;
; ../../../lib/ser_serialCommunication/src/ser_uart_wrapper32.vhd                          ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper32.vhd                   ;         ;
; ../../../lib/UFP_UsbFrontEndProtocol/exp/UFP_UsbFrontEndProtocol.vhd                     ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_UsbFrontEndProtocol.vhd              ;         ;
; ../../../lib/UFP_UsbFrontEndProtocol/exp/UFP_fw_version.vhd                              ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_fw_version.vhd                       ;         ;
; ../../../lib/UFP_UsbFrontEndProtocol/exp/UFP_Protocol.vhd                                ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_Protocol.vhd                         ;         ;
; ../../../lib/UFP_UsbFrontEndProtocol/src/UFP_Decoder.vhd                                 ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Decoder.vhd                          ;         ;
; ../../../lib/UFP_UsbFrontEndProtocol/src/UFP_Encoder_uart.vhd                            ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Encoder_uart.vhd                     ;         ;
; ../../../lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd                        ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd                 ;         ;
; ../../../lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SETGET_ACK.vhd                         ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SETGET_ACK.vhd                  ;         ;
; src/UGB_DATA_FIFO.vhd                                                                    ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/UGB_DATA_FIFO.vhd                      ;         ;
; src/UGB_GLOBAL_CONST.vhd                                                                 ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/UGB_GLOBAL_CONST.vhd                   ;         ;
; src/SERDES_TX_FIFO.vhd                                                                   ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/SERDES_TX_FIFO.vhd                     ;         ;
; src/SERDES_RX_FIFO.vhd                                                                   ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/SERDES_RX_FIFO.vhd                     ;         ;
; src/UGB_CFG_DPRAM.vhd                                                                    ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/UGB_CFG_DPRAM.vhd                      ;         ;
; src/L0_FIFO.vhd                                                                          ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/L0_FIFO.vhd                            ;         ;
; src/PLL_GPIO/PLL_60.vhd                                                                  ; yes             ; User Wizard-Generated File   ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/PLL_GPIO/PLL_60.vhd                    ; PLL_60  ;
; src/PLL_GPIO/PLL_60/PLL_60_0002.v                                                        ; yes             ; User Verilog HDL File        ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/PLL_GPIO/PLL_60/PLL_60_0002.v          ; PLL_60  ;
; src/USER_GET_CONFIG_RANGE_RD.vhd                                                         ; yes             ; User VHDL File               ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/USER_GET_CONFIG_RANGE_RD.vhd           ;         ;
; j:/vhdl_db/trunk/projets/pol_polar/fee_control/db/ip/gclk/gclk.v                         ; yes             ; Auto-Found Verilog HDL File  ; j:/vhdl_db/trunk/projets/pol_polar/fee_control/db/ip/gclk/gclk.v                          ; GCLK    ;
; j:/vhdl_db/trunk/projets/pol_polar/fee_control/db/ip/gclk/submodules/gclk_altclkctrl_0.v ; yes             ; Auto-Found Verilog HDL File  ; j:/vhdl_db/trunk/projets/pol_polar/fee_control/db/ip/gclk/submodules/gclk_altclkctrl_0.v  ; GCLK    ;
; altera_pll.v                                                                             ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altera_pll.v                            ;         ;
; altddio_out.tdf                                                                          ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altddio_out.tdf                         ;         ;
; aglobal180.inc                                                                           ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/aglobal180.inc                          ;         ;
; stratix_ddio.inc                                                                         ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/stratix_ddio.inc                        ;         ;
; cyclone_ddio.inc                                                                         ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/cyclone_ddio.inc                        ;         ;
; lpm_mux.inc                                                                              ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_mux.inc                             ;         ;
; stratix_lcell.inc                                                                        ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/stratix_lcell.inc                       ;         ;
; db/ddio_out_b2j.tdf                                                                      ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/ddio_out_b2j.tdf                        ;         ;
; dcfifo.tdf                                                                               ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf                              ;         ;
; lpm_counter.inc                                                                          ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_counter.inc                         ;         ;
; lpm_add_sub.inc                                                                          ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_add_sub.inc                         ;         ;
; altdpram.inc                                                                             ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altdpram.inc                            ;         ;
; a_graycounter.inc                                                                        ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_graycounter.inc                       ;         ;
; a_fefifo.inc                                                                             ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fefifo.inc                            ;         ;
; a_gray2bin.inc                                                                           ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_gray2bin.inc                          ;         ;
; dffpipe.inc                                                                              ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/dffpipe.inc                             ;         ;
; alt_sync_fifo.inc                                                                        ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/alt_sync_fifo.inc                       ;         ;
; lpm_compare.inc                                                                          ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_compare.inc                         ;         ;
; altsyncram_fifo.inc                                                                      ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram_fifo.inc                     ;         ;
; db/dcfifo_85n1.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_85n1.tdf                         ;         ;
; db/a_gray2bin_e9b.tdf                                                                    ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_gray2bin_e9b.tdf                      ;         ;
; db/a_graycounter_bg6.tdf                                                                 ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_bg6.tdf                   ;         ;
; db/a_graycounter_7ub.tdf                                                                 ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_7ub.tdf                   ;         ;
; db/altsyncram_cia1.tdf                                                                   ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_cia1.tdf                     ;         ;
; db/dffpipe_vu8.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_vu8.tdf                         ;         ;
; db/alt_synch_pipe_f9l.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_f9l.tdf                  ;         ;
; db/dffpipe_0v8.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_0v8.tdf                         ;         ;
; db/alt_synch_pipe_g9l.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_g9l.tdf                  ;         ;
; db/dffpipe_1v8.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_1v8.tdf                         ;         ;
; db/cmpr_vu5.tdf                                                                          ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cmpr_vu5.tdf                            ;         ;
; dcfifo_mixed_widths.tdf                                                                  ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo_mixed_widths.tdf                 ;         ;
; db/dcfifo_8tq1.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_8tq1.tdf                         ;         ;
; db/a_graycounter_cu6.tdf                                                                 ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_cu6.tdf                   ;         ;
; db/a_graycounter_9cc.tdf                                                                 ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_9cc.tdf                   ;         ;
; db/altsyncram_po91.tdf                                                                   ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_po91.tdf                     ;         ;
; db/alt_synch_pipe_unl.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_unl.tdf                  ;         ;
; db/dffpipe_fd9.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_fd9.tdf                         ;         ;
; db/dffpipe_ed9.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_ed9.tdf                         ;         ;
; db/alt_synch_pipe_vnl.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_vnl.tdf                  ;         ;
; db/dffpipe_gd9.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_gd9.tdf                         ;         ;
; db/cntr_osd.tdf                                                                          ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cntr_osd.tdf                            ;         ;
; db/dcfifo_a5q1.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_a5q1.tdf                         ;         ;
; db/a_graycounter_du6.tdf                                                                 ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_du6.tdf                   ;         ;
; db/a_graycounter_8cc.tdf                                                                 ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_8cc.tdf                   ;         ;
; db/altsyncram_qo91.tdf                                                                   ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_qo91.tdf                     ;         ;
; db/alt_synch_pipe_0ol.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_0ol.tdf                  ;         ;
; db/dffpipe_hd9.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_hd9.tdf                         ;         ;
; db/alt_synch_pipe_1ol.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_1ol.tdf                  ;         ;
; db/dffpipe_id9.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_id9.tdf                         ;         ;
; db/dcfifo_6tr1.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_6tr1.tdf                         ;         ;
; db/a_gray2bin_pab.tdf                                                                    ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_gray2bin_pab.tdf                      ;         ;
; db/a_graycounter_ov6.tdf                                                                 ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_ov6.tdf                   ;         ;
; db/a_graycounter_kdc.tdf                                                                 ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_kdc.tdf                   ;         ;
; db/altsyncram_m8d1.tdf                                                                   ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_m8d1.tdf                     ;         ;
; db/dffpipe_pe9.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_pe9.tdf                         ;         ;
; db/alt_synch_pipe_9pl.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_9pl.tdf                  ;         ;
; db/dffpipe_qe9.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_qe9.tdf                         ;         ;
; db/alt_synch_pipe_apl.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_apl.tdf                  ;         ;
; db/dffpipe_re9.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_re9.tdf                         ;         ;
; db/cmpr_a06.tdf                                                                          ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cmpr_a06.tdf                            ;         ;
; altsyncram.tdf                                                                           ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf                          ;         ;
; stratix_ram_block.inc                                                                    ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/stratix_ram_block.inc                   ;         ;
; lpm_decode.inc                                                                           ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/lpm_decode.inc                          ;         ;
; a_rdenreg.inc                                                                            ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_rdenreg.inc                           ;         ;
; altrom.inc                                                                               ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altrom.inc                              ;         ;
; altram.inc                                                                               ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/altram.inc                              ;         ;
; db/altsyncram_s1v3.tdf                                                                   ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_s1v3.tdf                     ;         ;
; db/dcfifo_t7q1.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_t7q1.tdf                         ;         ;
; db/altsyncram_s5d1.tdf                                                                   ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_s5d1.tdf                     ;         ;
; db/alt_synch_pipe_bpl.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_bpl.tdf                  ;         ;
; db/dffpipe_se9.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_se9.tdf                         ;         ;
; db/alt_synch_pipe_cpl.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_cpl.tdf                  ;         ;
; db/dffpipe_te9.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_te9.tdf                         ;         ;
; db/dcfifo_12q1.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_12q1.tdf                         ;         ;
; db/a_graycounter_bu6.tdf                                                                 ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_bu6.tdf                   ;         ;
; db/a_graycounter_7cc.tdf                                                                 ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_7cc.tdf                   ;         ;
; db/altsyncram_03d1.tdf                                                                   ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_03d1.tdf                     ;         ;
; db/alt_synch_pipe_snl.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_snl.tdf                  ;         ;
; db/dffpipe_dd9.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_dd9.tdf                         ;         ;
; db/alt_synch_pipe_tnl.tdf                                                                ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_tnl.tdf                  ;         ;
; db/dffpipe_jd9.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_jd9.tdf                         ;         ;
; db/cmpr_tu5.tdf                                                                          ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cmpr_tu5.tdf                            ;         ;
; scfifo.tdf                                                                               ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/scfifo.tdf                              ;         ;
; a_regfifo.inc                                                                            ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_regfifo.inc                           ;         ;
; a_dpfifo.inc                                                                             ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_dpfifo.inc                            ;         ;
; a_i2fifo.inc                                                                             ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_i2fifo.inc                            ;         ;
; a_fffifo.inc                                                                             ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_fffifo.inc                            ;         ;
; a_f2fifo.inc                                                                             ; yes             ; Megafunction                 ; c:/intelfpga/18.0/quartus/libraries/megafunctions/a_f2fifo.inc                            ;         ;
; db/scfifo_3e91.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/scfifo_3e91.tdf                         ;         ;
; db/a_dpfifo_ak91.tdf                                                                     ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_dpfifo_ak91.tdf                       ;         ;
; db/altsyncram_j0i1.tdf                                                                   ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_j0i1.tdf                     ;         ;
; db/cmpr_5l8.tdf                                                                          ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cmpr_5l8.tdf                            ;         ;
; db/cntr_igb.tdf                                                                          ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cntr_igb.tdf                            ;         ;
; db/cntr_vg7.tdf                                                                          ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cntr_vg7.tdf                            ;         ;
; db/cntr_jgb.tdf                                                                          ; yes             ; Auto-Generated Megafunction  ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cntr_jgb.tdf                            ;         ;
+------------------------------------------------------------------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------------+---------+


+----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary              ;
+---------------------------------------------+------------+
; Resource                                    ; Usage      ;
+---------------------------------------------+------------+
; Estimate of Logic utilization (ALMs needed) ; 3174       ;
;                                             ;            ;
; Combinational ALUT usage for logic          ; 1927       ;
;     -- 7 input functions                    ; 10         ;
;     -- 6 input functions                    ; 950        ;
;     -- 5 input functions                    ; 203        ;
;     -- 4 input functions                    ; 235        ;
;     -- <=3 input functions                  ; 529        ;
;                                             ;            ;
; Dedicated logic registers                   ; 5317       ;
;                                             ;            ;
; I/O pins                                    ; 207        ;
; I/O registers                               ; 2          ;
; Total MLAB memory bits                      ; 0          ;
; Total block memory bits                     ; 67776      ;
;                                             ;            ;
; Total DSP Blocks                            ; 0          ;
;                                             ;            ;
; Total PLLs                                  ; 4          ;
;     -- PLLs                                 ; 4          ;
;                                             ;            ;
; Maximum fan-out node                        ; s_clk_main ;
; Maximum fan-out                             ; 5232       ;
; Total fan-out                               ; 32326      ;
; Average fan-out                             ; 4.11       ;
+---------------------------------------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+---------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+--------------+
; Compilation Hierarchy Node                                          ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                           ; Entity Name                  ; Library Name ;
+---------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+--------------+
; |FEE_Control                                                        ; 1927 (121)          ; 5317 (89)                 ; 67776             ; 0          ; 207  ; 0            ; |FEE_Control                                                                                                                                                                                                                                                  ; FEE_Control                  ; work         ;
;    |L0_FIFO:C_L0_FIFO|                                              ; 34 (0)              ; 29 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FEE_Control|L0_FIFO:C_L0_FIFO                                                                                                                                                                                                                                ; L0_FIFO                      ; work         ;
;       |scfifo:scfifo_component|                                     ; 34 (0)              ; 29 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FEE_Control|L0_FIFO:C_L0_FIFO|scfifo:scfifo_component                                                                                                                                                                                                        ; scfifo                       ; work         ;
;          |scfifo_3e91:auto_generated|                               ; 34 (0)              ; 29 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FEE_Control|L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated                                                                                                                                                                             ; scfifo_3e91                  ; work         ;
;             |a_dpfifo_ak91:dpfifo|                                  ; 34 (17)             ; 29 (12)                   ; 2048              ; 0          ; 0    ; 0            ; |FEE_Control|L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo                                                                                                                                                        ; a_dpfifo_ak91                ; work         ;
;                |altsyncram_j0i1:FIFOram|                            ; 0 (0)               ; 0 (0)                     ; 2048              ; 0          ; 0    ; 0            ; |FEE_Control|L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo|altsyncram_j0i1:FIFOram                                                                                                                                ; altsyncram_j0i1              ; work         ;
;                |cntr_igb:rd_ptr_msb|                                ; 5 (5)               ; 5 (5)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo|cntr_igb:rd_ptr_msb                                                                                                                                    ; cntr_igb                     ; work         ;
;                |cntr_jgb:wr_ptr|                                    ; 6 (6)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo|cntr_jgb:wr_ptr                                                                                                                                        ; cntr_jgb                     ; work         ;
;                |cntr_vg7:usedw_counter|                             ; 6 (6)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo|cntr_vg7:usedw_counter                                                                                                                                 ; cntr_vg7                     ; work         ;
;    |PLL_60:C_PLL|                                                   ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|PLL_60:C_PLL                                                                                                                                                                                                                                     ; PLL_60                       ; pll_60       ;
;       |PLL_60_0002:pll_60_inst|                                     ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|PLL_60:C_PLL|PLL_60_0002:pll_60_inst                                                                                                                                                                                                             ; PLL_60_0002                  ; PLL_60       ;
;          |altera_pll:altera_pll_i|                                  ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|PLL_60:C_PLL|PLL_60_0002:pll_60_inst|altera_pll:altera_pll_i                                                                                                                                                                                     ; altera_pll                   ; work         ;
;    |SERDES_RX_FIFO:RX_FIFO|                                         ; 25 (0)              ; 47 (0)                    ; 128               ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_RX_FIFO:RX_FIFO                                                                                                                                                                                                                           ; SERDES_RX_FIFO               ; work         ;
;       |dcfifo:dcfifo_component|                                     ; 25 (0)              ; 47 (0)                    ; 128               ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component                                                                                                                                                                                                   ; dcfifo                       ; work         ;
;          |dcfifo_12q1:auto_generated|                               ; 25 (6)              ; 47 (15)                   ; 128               ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated                                                                                                                                                                        ; dcfifo_12q1                  ; work         ;
;             |a_graycounter_7cc:wrptr_g1p|                           ; 6 (6)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|a_graycounter_7cc:wrptr_g1p                                                                                                                                            ; a_graycounter_7cc            ; work         ;
;             |a_graycounter_bu6:rdptr_g1p|                           ; 7 (7)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|a_graycounter_bu6:rdptr_g1p                                                                                                                                            ; a_graycounter_bu6            ; work         ;
;             |alt_synch_pipe_snl:rs_dgwp|                            ; 0 (0)               ; 10 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp                                                                                                                                             ; alt_synch_pipe_snl           ; work         ;
;                |dffpipe_dd9:dffpipe10|                              ; 0 (0)               ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe10                                                                                                                       ; dffpipe_dd9                  ; work         ;
;             |alt_synch_pipe_tnl:ws_dgrp|                            ; 0 (0)               ; 10 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp                                                                                                                                             ; alt_synch_pipe_tnl           ; work         ;
;                |dffpipe_jd9:dffpipe13|                              ; 0 (0)               ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_jd9:dffpipe13                                                                                                                       ; dffpipe_jd9                  ; work         ;
;             |altsyncram_03d1:fifo_ram|                              ; 0 (0)               ; 0 (0)                     ; 128               ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|altsyncram_03d1:fifo_ram                                                                                                                                               ; altsyncram_03d1              ; work         ;
;             |cmpr_tu5:rdempty_eq_comp|                              ; 3 (3)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|cmpr_tu5:rdempty_eq_comp                                                                                                                                               ; cmpr_tu5                     ; work         ;
;             |cmpr_tu5:wrfull_eq_comp|                               ; 3 (3)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|cmpr_tu5:wrfull_eq_comp                                                                                                                                                ; cmpr_tu5                     ; work         ;
;    |SERDES_TX_FIFO:TX_FIFO|                                         ; 51 (0)              ; 105 (0)                   ; 9216              ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_TX_FIFO:TX_FIFO                                                                                                                                                                                                                           ; SERDES_TX_FIFO               ; work         ;
;       |dcfifo:dcfifo_component|                                     ; 51 (0)              ; 105 (0)                   ; 9216              ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component                                                                                                                                                                                                   ; dcfifo                       ; work         ;
;          |dcfifo_t7q1:auto_generated|                               ; 51 (5)              ; 105 (33)                  ; 9216              ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated                                                                                                                                                                        ; dcfifo_t7q1                  ; work         ;
;             |a_graycounter_kdc:wrptr_g1p|                           ; 17 (17)             ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|a_graycounter_kdc:wrptr_g1p                                                                                                                                            ; a_graycounter_kdc            ; work         ;
;             |a_graycounter_ov6:rdptr_g1p|                           ; 18 (18)             ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|a_graycounter_ov6:rdptr_g1p                                                                                                                                            ; a_graycounter_ov6            ; work         ;
;             |alt_synch_pipe_bpl:rs_dgwp|                            ; 0 (0)               ; 22 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp                                                                                                                                             ; alt_synch_pipe_bpl           ; work         ;
;                |dffpipe_se9:dffpipe6|                               ; 0 (0)               ; 22 (22)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6                                                                                                                        ; dffpipe_se9                  ; work         ;
;             |alt_synch_pipe_cpl:ws_dgrp|                            ; 0 (0)               ; 22 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp                                                                                                                                             ; alt_synch_pipe_cpl           ; work         ;
;                |dffpipe_te9:dffpipe9|                               ; 0 (0)               ; 22 (22)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9                                                                                                                        ; dffpipe_te9                  ; work         ;
;             |altsyncram_s5d1:fifo_ram|                              ; 2 (2)               ; 0 (0)                     ; 9216              ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|altsyncram_s5d1:fifo_ram                                                                                                                                               ; altsyncram_s5d1              ; work         ;
;             |cmpr_a06:rdempty_eq_comp|                              ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|cmpr_a06:rdempty_eq_comp                                                                                                                                               ; cmpr_a06                     ; work         ;
;             |cmpr_a06:wrfull_eq_comp|                               ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|cmpr_a06:wrfull_eq_comp                                                                                                                                                ; cmpr_a06                     ; work         ;
;    |UFP_USER_SETGET_ACK:C_GET_ACK|                                  ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_USER_SETGET_ACK:C_GET_ACK                                                                                                                                                                                                                    ; UFP_USER_SETGET_ACK          ; work         ;
;    |UFP_WRAPPER_USB_UART:C_WRAPPER_USB|                             ; 680 (5)             ; 611 (1)                   ; 6208              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB                                                                                                                                                                                                               ; UFP_WRAPPER_USB_UART         ; work         ;
;       |UFP_DECODER:C_DECODER|                                       ; 241 (241)           ; 107 (107)                 ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER                                                                                                                                                                                         ; UFP_DECODER                  ; work         ;
;       |UFP_ENCODER_UART:C_ENCODER|                                  ; 156 (156)           ; 120 (120)                 ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER                                                                                                                                                                                    ; UFP_ENCODER_UART             ; work         ;
;       |USB_L2_TX_FIFO:C_FIFO_READOUT_TX|                            ; 52 (0)              ; 81 (0)                    ; 2112              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX                                                                                                                                                                              ; USB_L2_TX_FIFO               ; work         ;
;          |dcfifo:dcfifo_component|                                  ; 52 (0)              ; 81 (0)                    ; 2112              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component                                                                                                                                                      ; dcfifo                       ; work         ;
;             |dcfifo_85n1:auto_generated|                            ; 52 (12)             ; 81 (21)                   ; 2112              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated                                                                                                                           ; dcfifo_85n1                  ; work         ;
;                |a_gray2bin_e9b:wrptr_g_gray2bin|                    ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_gray2bin_e9b:wrptr_g_gray2bin                                                                                           ; a_gray2bin_e9b               ; work         ;
;                |a_gray2bin_e9b:ws_dgrp_gray2bin|                    ; 6 (6)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_gray2bin_e9b:ws_dgrp_gray2bin                                                                                           ; a_gray2bin_e9b               ; work         ;
;                |a_graycounter_7ub:wrptr_g1p|                        ; 10 (10)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_7ub:wrptr_g1p                                                                                               ; a_graycounter_7ub            ; work         ;
;                |a_graycounter_bg6:rdptr_g1p|                        ; 11 (11)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_bg6:rdptr_g1p                                                                                               ; a_graycounter_bg6            ; work         ;
;                |alt_synch_pipe_f9l:rs_dgwp|                         ; 0 (0)               ; 14 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp                                                                                                ; alt_synch_pipe_f9l           ; work         ;
;                   |dffpipe_0v8:dffpipe13|                           ; 0 (0)               ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13                                                                          ; dffpipe_0v8                  ; work         ;
;                |alt_synch_pipe_g9l:ws_dgrp|                         ; 0 (0)               ; 14 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp                                                                                                ; alt_synch_pipe_g9l           ; work         ;
;                   |dffpipe_1v8:dffpipe16|                           ; 0 (0)               ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16                                                                          ; dffpipe_1v8                  ; work         ;
;                |altsyncram_cia1:fifo_ram|                           ; 0 (0)               ; 0 (0)                     ; 2112              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|altsyncram_cia1:fifo_ram                                                                                                  ; altsyncram_cia1              ; work         ;
;                |cmpr_vu5:rdempty_eq_comp|                           ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|cmpr_vu5:rdempty_eq_comp                                                                                                  ; cmpr_vu5                     ; work         ;
;                |cmpr_vu5:wrfull_eq_comp|                            ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|cmpr_vu5:wrfull_eq_comp                                                                                                   ; cmpr_vu5                     ; work         ;
;                |dffpipe_vu8:ws_brp|                                 ; 0 (0)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_brp                                                                                                        ; dffpipe_vu8                  ; work         ;
;                |dffpipe_vu8:ws_bwp|                                 ; 0 (0)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_bwp                                                                                                        ; dffpipe_vu8                  ; work         ;
;       |USB_USB_Reader:C_USB|                                        ; 38 (38)             ; 63 (63)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB                                                                                                                                                                                          ; USB_USB_Reader               ; work         ;
;          |USB_UC_PCLK:C_UC_PCLK|                                    ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK                                                                                                                                                                    ; USB_UC_PCLK                  ; work         ;
;             |altddio_out:ALTDDIO_OUT_component|                     ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component                                                                                                                                  ; altddio_out                  ; work         ;
;                |ddio_out_b2j:auto_generated|                        ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated                                                                                                      ; ddio_out_b2j                 ; work         ;
;       |ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|                          ; 34 (4)              ; 21 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC                                                                                                                                                                            ; ser_crc_pol16_DIN16_D4_1a2eb ; work         ;
;          |ser_crc:C_CRC|                                            ; 30 (30)             ; 21 (21)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC                                                                                                                                                              ; ser_crc                      ; work         ;
;       |ser_uart_wrapper:C_UART|                                     ; 154 (0)             ; 218 (0)                   ; 4096              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART                                                                                                                                                                                       ; ser_uart_wrapper             ; work         ;
;          |ser_uart_wrapper32:\g32:u1|                               ; 154 (0)             ; 218 (0)                   ; 4096              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1                                                                                                                                                            ; ser_uart_wrapper32           ; work         ;
;             |SER_UART_FIFO_RX32:C_FIFO_RX|                          ; 40 (0)              ; 73 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX                                                                                                                               ; SER_UART_FIFO_RX32           ; work         ;
;                |dcfifo_mixed_widths:dcfifo_mixed_widths_component|  ; 40 (0)              ; 73 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component                                                                             ; dcfifo_mixed_widths          ; work         ;
;                   |dcfifo_a5q1:auto_generated|                      ; 40 (6)              ; 73 (23)                   ; 2048              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated                                                  ; dcfifo_a5q1                  ; work         ;
;                      |a_graycounter_8cc:wrptr_g1p|                  ; 11 (11)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_8cc:wrptr_g1p                      ; a_graycounter_8cc            ; work         ;
;                      |a_graycounter_du6:rdptr_g1p|                  ; 11 (11)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_du6:rdptr_g1p                      ; a_graycounter_du6            ; work         ;
;                      |alt_synch_pipe_0ol:rs_dgwp|                   ; 0 (0)               ; 14 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp                       ; alt_synch_pipe_0ol           ; work         ;
;                         |dffpipe_hd9:dffpipe12|                     ; 0 (0)               ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12 ; dffpipe_hd9                  ; work         ;
;                      |alt_synch_pipe_1ol:ws_dgrp|                   ; 0 (0)               ; 14 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp                       ; alt_synch_pipe_1ol           ; work         ;
;                         |dffpipe_id9:dffpipe15|                     ; 0 (0)               ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15 ; dffpipe_id9                  ; work         ;
;                      |altsyncram_qo91:fifo_ram|                     ; 0 (0)               ; 0 (0)                     ; 2048              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|altsyncram_qo91:fifo_ram                         ; altsyncram_qo91              ; work         ;
;                      |cmpr_vu5:rdempty_eq_comp|                     ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|cmpr_vu5:rdempty_eq_comp                         ; cmpr_vu5                     ; work         ;
;                      |cmpr_vu5:wrfull_eq_comp|                      ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|cmpr_vu5:wrfull_eq_comp                          ; cmpr_vu5                     ; work         ;
;                      |cntr_osd:cntr_b|                              ; 4 (4)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|cntr_osd:cntr_b                                  ; cntr_osd                     ; work         ;
;             |SER_UART_FIFO_TX32:C_FIFO_TX|                          ; 57 (0)              ; 83 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX                                                                                                                               ; SER_UART_FIFO_TX32           ; work         ;
;                |dcfifo_mixed_widths:dcfifo_mixed_widths_component|  ; 57 (0)              ; 83 (0)                    ; 2048              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component                                                                             ; dcfifo_mixed_widths          ; work         ;
;                   |dcfifo_8tq1:auto_generated|                      ; 57 (11)             ; 83 (21)                   ; 2048              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated                                                  ; dcfifo_8tq1                  ; work         ;
;                      |a_gray2bin_e9b:wrptr_g_gray2bin|              ; 6 (6)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_gray2bin_e9b:wrptr_g_gray2bin                  ; a_gray2bin_e9b               ; work         ;
;                      |a_gray2bin_e9b:ws_dgrp_gray2bin|              ; 6 (6)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_gray2bin_e9b:ws_dgrp_gray2bin                  ; a_gray2bin_e9b               ; work         ;
;                      |a_graycounter_9cc:wrptr_g1p|                  ; 10 (10)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_9cc:wrptr_g1p                      ; a_graycounter_9cc            ; work         ;
;                      |a_graycounter_cu6:rdptr_g1p|                  ; 11 (11)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_cu6:rdptr_g1p                      ; a_graycounter_cu6            ; work         ;
;                      |alt_synch_pipe_unl:rs_dgwp|                   ; 0 (0)               ; 14 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp                       ; alt_synch_pipe_unl           ; work         ;
;                         |dffpipe_fd9:dffpipe12|                     ; 0 (0)               ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12 ; dffpipe_fd9                  ; work         ;
;                      |alt_synch_pipe_vnl:ws_dgrp|                   ; 0 (0)               ; 14 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp                       ; alt_synch_pipe_vnl           ; work         ;
;                         |dffpipe_gd9:dffpipe16|                     ; 0 (0)               ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16 ; dffpipe_gd9                  ; work         ;
;                      |altsyncram_po91:fifo_ram|                     ; 0 (0)               ; 0 (0)                     ; 2048              ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|altsyncram_po91:fifo_ram                         ; altsyncram_po91              ; work         ;
;                      |cmpr_vu5:rdempty_eq_comp|                     ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|cmpr_vu5:rdempty_eq_comp                         ; cmpr_vu5                     ; work         ;
;                      |cmpr_vu5:wrfull_eq_comp|                      ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|cmpr_vu5:wrfull_eq_comp                          ; cmpr_vu5                     ; work         ;
;                      |cntr_osd:cntr_b|                              ; 5 (5)               ; 2 (2)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|cntr_osd:cntr_b                                  ; cntr_osd                     ; work         ;
;                      |dffpipe_ed9:ws_brp|                           ; 0 (0)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_brp                               ; dffpipe_ed9                  ; work         ;
;                      |dffpipe_ed9:ws_bwp|                           ; 0 (0)               ; 6 (6)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_bwp                               ; dffpipe_ed9                  ; work         ;
;             |ser_uart:C_UART|                                       ; 57 (2)              ; 62 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART                                                                                                                                            ; ser_uart                     ; work         ;
;                |ser_uart_bdgen:\g_dbgen:C_BDGEN|                    ; 10 (10)             ; 10 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_bdgen:\g_dbgen:C_BDGEN                                                                                                            ; ser_uart_bdgen               ; work         ;
;                |ser_uart_deser:C_DESER|                             ; 21 (18)             ; 31 (28)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER                                                                                                                     ; ser_uart_deser               ; work         ;
;                   |ser_data_5_bits_filter:C_FILTER_SIN|             ; 3 (3)               ; 3 (3)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|ser_data_5_bits_filter:C_FILTER_SIN                                                                                 ; ser_data_5_bits_filter       ; work         ;
;                |ser_uart_ser:C_SER|                                 ; 24 (24)             ; 21 (21)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER                                                                                                                         ; ser_uart_ser                 ; work         ;
;    |UGB_CFG_DPRAM:C_DPRAM|                                          ; 0 (0)               ; 0 (0)                     ; 16384             ; 0          ; 0    ; 0            ; |FEE_Control|UGB_CFG_DPRAM:C_DPRAM                                                                                                                                                                                                                            ; UGB_CFG_DPRAM                ; work         ;
;       |altsyncram:altsyncram_component|                             ; 0 (0)               ; 0 (0)                     ; 16384             ; 0          ; 0    ; 0            ; |FEE_Control|UGB_CFG_DPRAM:C_DPRAM|altsyncram:altsyncram_component                                                                                                                                                                                            ; altsyncram                   ; work         ;
;          |altsyncram_s1v3:auto_generated|                           ; 0 (0)               ; 0 (0)                     ; 16384             ; 0          ; 0    ; 0            ; |FEE_Control|UGB_CFG_DPRAM:C_DPRAM|altsyncram:altsyncram_component|altsyncram_s1v3:auto_generated                                                                                                                                                             ; altsyncram_s1v3              ; work         ;
;    |UGB_DATA_FIFO:C_FIFO|                                           ; 59 (0)              ; 105 (0)                   ; 33792             ; 0          ; 0    ; 0            ; |FEE_Control|UGB_DATA_FIFO:C_FIFO                                                                                                                                                                                                                             ; UGB_DATA_FIFO                ; work         ;
;       |dcfifo:dcfifo_component|                                     ; 59 (0)              ; 105 (0)                   ; 33792             ; 0          ; 0    ; 0            ; |FEE_Control|UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component                                                                                                                                                                                                     ; dcfifo                       ; work         ;
;          |dcfifo_6tr1:auto_generated|                               ; 59 (4)              ; 105 (33)                  ; 33792             ; 0          ; 0    ; 0            ; |FEE_Control|UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated                                                                                                                                                                          ; dcfifo_6tr1                  ; work         ;
;             |a_graycounter_kdc:wrptr_g1p|                           ; 17 (17)             ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|a_graycounter_kdc:wrptr_g1p                                                                                                                                              ; a_graycounter_kdc            ; work         ;
;             |a_graycounter_ov6:rdptr_g1p|                           ; 29 (29)             ; 14 (14)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|a_graycounter_ov6:rdptr_g1p                                                                                                                                              ; a_graycounter_ov6            ; work         ;
;             |alt_synch_pipe_9pl:rs_dgwp|                            ; 0 (0)               ; 22 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp                                                                                                                                               ; alt_synch_pipe_9pl           ; work         ;
;                |dffpipe_qe9:dffpipe13|                              ; 0 (0)               ; 22 (22)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13                                                                                                                         ; dffpipe_qe9                  ; work         ;
;             |alt_synch_pipe_apl:ws_dgrp|                            ; 0 (0)               ; 22 (0)                    ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp                                                                                                                                               ; alt_synch_pipe_apl           ; work         ;
;                |dffpipe_re9:dffpipe16|                              ; 0 (0)               ; 22 (22)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16                                                                                                                         ; dffpipe_re9                  ; work         ;
;             |altsyncram_m8d1:fifo_ram|                              ; 0 (0)               ; 0 (0)                     ; 33792             ; 0          ; 0    ; 0            ; |FEE_Control|UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|altsyncram_m8d1:fifo_ram                                                                                                                                                 ; altsyncram_m8d1              ; work         ;
;             |cmpr_a06:rdempty_eq_comp|                              ; 5 (5)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|cmpr_a06:rdempty_eq_comp                                                                                                                                                 ; cmpr_a06                     ; work         ;
;             |cmpr_a06:wrfull_eq_comp|                               ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|cmpr_a06:wrfull_eq_comp                                                                                                                                                  ; cmpr_a06                     ; work         ;
;    |USER_GET_CONFIG_RANGE_RD:C_HOUSEKEEPING_USER_GET|               ; 40 (40)             ; 20 (20)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|USER_GET_CONFIG_RANGE_RD:C_HOUSEKEEPING_USER_GET                                                                                                                                                                                                 ; USER_GET_CONFIG_RANGE_RD     ; work         ;
;    |USER_GET_CONFIG_RANGE_RD:C_PEDESTALS_USER_GET|                  ; 682 (682)           ; 20 (20)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|USER_GET_CONFIG_RANGE_RD:C_PEDESTALS_USER_GET                                                                                                                                                                                                    ; USER_GET_CONFIG_RANGE_RD     ; work         ;
;    |fee_controller:C_FEECONTROLLER|                                 ; 162 (162)           ; 4217 (4217)               ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|fee_controller:C_FEECONTROLLER                                                                                                                                                                                                                   ; fee_controller               ; work         ;
;    |serdes:SERDES|                                                  ; 72 (6)              ; 74 (10)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|serdes:SERDES                                                                                                                                                                                                                                    ; serdes                       ; work         ;
;       |GCLK:RxClk_Buf|                                              ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|serdes:SERDES|GCLK:RxClk_Buf                                                                                                                                                                                                                     ; GCLK                         ; GCLK         ;
;          |GCLK_altclkctrl_0:altclkctrl_0|                           ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|serdes:SERDES|GCLK:RxClk_Buf|GCLK_altclkctrl_0:altclkctrl_0                                                                                                                                                                                      ; GCLK_altclkctrl_0            ; GCLK         ;
;             |GCLK_altclkctrl_0_sub:GCLK_altclkctrl_0_sub_component| ; 0 (0)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|serdes:SERDES|GCLK:RxClk_Buf|GCLK_altclkctrl_0:altclkctrl_0|GCLK_altclkctrl_0_sub:GCLK_altclkctrl_0_sub_component                                                                                                                                ; GCLK_altclkctrl_0_sub        ; GCLK         ;
;       |deserializer:SERIAL_RX|                                      ; 35 (17)             ; 37 (27)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|serdes:SERDES|deserializer:SERIAL_RX                                                                                                                                                                                                             ; deserializer                 ; work         ;
;          |decoder_4b5b:LSBDECODE|                                   ; 9 (9)               ; 5 (5)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|serdes:SERDES|deserializer:SERIAL_RX|decoder_4b5b:LSBDECODE                                                                                                                                                                                      ; decoder_4b5b                 ; work         ;
;          |decoder_4b5b:MSBDECODE|                                   ; 9 (9)               ; 5 (5)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|serdes:SERDES|deserializer:SERIAL_RX|decoder_4b5b:MSBDECODE                                                                                                                                                                                      ; decoder_4b5b                 ; work         ;
;       |serializer:SERIAL_TX|                                        ; 31 (21)             ; 27 (17)                   ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|serdes:SERDES|serializer:SERIAL_TX                                                                                                                                                                                                               ; serializer                   ; work         ;
;          |encoder_4b5b:LSBCODER|                                    ; 5 (5)               ; 5 (5)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|serdes:SERDES|serializer:SERIAL_TX|encoder_4b5b:LSBCODER                                                                                                                                                                                         ; encoder_4b5b                 ; work         ;
;          |encoder_4b5b:MSBCODER|                                    ; 5 (5)               ; 5 (5)                     ; 0                 ; 0          ; 0    ; 0            ; |FEE_Control|serdes:SERDES|serializer:SERIAL_TX|encoder_4b5b:MSBCODER                                                                                                                                                                                         ; encoder_4b5b                 ; work         ;
+---------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                                                         ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; Name                                                                                                                                                                                                                                ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo|altsyncram_j0i1:FIFOram|ALTSYNCRAM                                                                                                        ; AUTO ; Simple Dual Port ; 64           ; 32           ; 64           ; 32           ; 2048  ; None ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|altsyncram_03d1:fifo_ram|ALTSYNCRAM                                                                                                                       ; AUTO ; Simple Dual Port ; 16           ; 8            ; 16           ; 8            ; 128   ; None ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|altsyncram_s5d1:fifo_ram|ALTSYNCRAM                                                                                                                       ; AUTO ; Simple Dual Port ; 1024         ; 9            ; 1024         ; 9            ; 9216  ; None ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|altsyncram_cia1:fifo_ram|ALTSYNCRAM                                                                          ; AUTO ; Simple Dual Port ; 64           ; 33           ; 64           ; 33           ; 2112  ; None ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|altsyncram_qo91:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 256          ; 8            ; 64           ; 32           ; 2048  ; None ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|altsyncram_po91:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64           ; 32           ; 256          ; 8            ; 2048  ; None ;
; UGB_CFG_DPRAM:C_DPRAM|altsyncram:altsyncram_component|altsyncram_s1v3:auto_generated|ALTSYNCRAM                                                                                                                                     ; AUTO ; Simple Dual Port ; 1024         ; 16           ; 1024         ; 16           ; 16384 ; None ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|altsyncram_m8d1:fifo_ram|ALTSYNCRAM                                                                                                                         ; AUTO ; Simple Dual Port ; 1024         ; 33           ; 1024         ; 33           ; 33792 ; None ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                                        ;
+--------+--------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                                                                                                                 ; IP Include File                                                            ;
+--------+--------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------+
; Altera ; RAM: 2-PORT  ; 18.0    ; N/A          ; N/A          ; |FEE_Control|UGB_CFG_DPRAM:C_DPRAM                                                                                              ; src/UGB_CFG_DPRAM.vhd                                                      ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FEE_Control|UGB_DATA_FIFO:C_FIFO                                                                                               ; src/UGB_DATA_FIFO.vhd                                                      ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FEE_Control|L0_FIFO:C_L0_FIFO                                                                                                  ; src/L0_FIFO.vhd                                                            ;
; Altera ; altera_pll   ; 18.0    ; N/A          ; N/A          ; |FEE_Control|PLL_60:C_PLL                                                                                                       ; src/PLL_GPIO/PLL_60.vhd                                                    ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX                                                ; ../../../lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd                     ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX ; ../../../lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX ; ../../../lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd ;
; Altera ; ALTDDIO_OUT  ; 18.0    ; N/A          ; N/A          ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK                                      ; ../../../lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd                        ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FEE_Control|SERDES_RX_FIFO:RX_FIFO                                                                                             ; src/SERDES_RX_FIFO.vhd                                                     ;
; N/A    ; altclkctrl   ; 18.0    ; N/A          ; N/A          ; |FEE_Control|serdes:SERDES|GCLK:RxClk_Buf                                                                                       ; J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/GCLK.qsys                   ;
; Altera ; FIFO         ; 18.0    ; N/A          ; N/A          ; |FEE_Control|SERDES_TX_FIFO:TX_FIFO                                                                                             ; src/SERDES_TX_FIFO.vhd                                                     ;
+--------+--------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|s_state                                                                      ;
+-------------------+--------------+------------------+-------------------+------------------+--------------+
; Name              ; s_state.STOP ; s_state.WAIT_EOP ; s_state.DATABREAK ; s_state.WAITDATA ; s_state.IDLE ;
+-------------------+--------------+------------------+-------------------+------------------+--------------+
; s_state.IDLE      ; 0            ; 0                ; 0                 ; 0                ; 0            ;
; s_state.WAITDATA  ; 0            ; 0                ; 0                 ; 1                ; 1            ;
; s_state.DATABREAK ; 0            ; 0                ; 1                 ; 0                ; 1            ;
; s_state.WAIT_EOP  ; 0            ; 1                ; 0                 ; 0                ; 1            ;
; s_state.STOP      ; 1            ; 0                ; 0                 ; 0                ; 1            ;
+-------------------+--------------+------------------+-------------------+------------------+--------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|fee_controller:C_FEECONTROLLER|s_tx_state                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+------------------------------+---------------------------+-------------------------+-------------------------+--------------------------+-------------------------+------------------------+-------------------------+------------------------+---------------------------+----------------------+--------------------+-----------------------------+---------------------------+---------------------------+----------------------------+----------------------------+--------------------------+--------------------------+-----------------------------+---------------------------+-------------------------+-------------------------+--------------------------+--------------------------+--------------------------+------------------------+-------------------------+------------------------+---------------------------+------------------------------+----------------------------+----------------------------+---------------------------+----------------------------+---------------------------+------------------------------+-----------------+
; Name                         ; s_tx_state.SET_ACQ_ACK_OK ; s_tx_state.SET_ACQ_WACK ; s_tx_state.SET_ACQ_ENDW ; s_tx_state.SET_ACQ_DATA1 ; s_tx_state.SET_ACQ_DATA ; s_tx_state.SET_ACQ_LEN ; s_tx_state.SET_ACQ_ADDR ; s_tx_state.SET_ACQ_CMD ; s_tx_state.SET_ACQ_STARTW ; s_tx_state.REQ_ERROR ; s_tx_state.REQ_ACK ; s_tx_state.APPLY_CFG_ACK_OK ; s_tx_state.APPLY_CFG_WACK ; s_tx_state.APPLY_CFG_ENDW ; s_tx_state.APPLY_CFG_DATA1 ; s_tx_state.APPLY_CFG_DATA0 ; s_tx_state.APPLY_CFG_LEN ; s_tx_state.APPLY_CFG_CMD ; s_tx_state.APPLY_CFG_STARTW ; s_tx_state.SET_CFG_ACK_OK ; s_tx_state.SET_CFG_WACK ; s_tx_state.SET_CFG_ENDW ; s_tx_state.SET_CFG_FETCH ; s_tx_state.SET_CFG_DATA1 ; s_tx_state.SET_CFG_DATA0 ; s_tx_state.SET_CFG_LEN ; s_tx_state.SET_CFG_ADDR ; s_tx_state.SET_CFG_CMD ; s_tx_state.SET_CFG_STARTW ; s_tx_state.GET_STATUS_ACK_OK ; s_tx_state.GET_STATUS_WACK ; s_tx_state.GET_STATUS_ENDW ; s_tx_state.GET_STATUS_LEN ; s_tx_state.GET_STATUS_ADDR ; s_tx_state.GET_STATUS_CMD ; s_tx_state.GET_STATUS_STARTW ; s_tx_state.IDLE ;
+------------------------------+---------------------------+-------------------------+-------------------------+--------------------------+-------------------------+------------------------+-------------------------+------------------------+---------------------------+----------------------+--------------------+-----------------------------+---------------------------+---------------------------+----------------------------+----------------------------+--------------------------+--------------------------+-----------------------------+---------------------------+-------------------------+-------------------------+--------------------------+--------------------------+--------------------------+------------------------+-------------------------+------------------------+---------------------------+------------------------------+----------------------------+----------------------------+---------------------------+----------------------------+---------------------------+------------------------------+-----------------+
; s_tx_state.IDLE              ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 0               ;
; s_tx_state.GET_STATUS_STARTW ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 1                            ; 1               ;
; s_tx_state.GET_STATUS_CMD    ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 1                         ; 0                            ; 1               ;
; s_tx_state.GET_STATUS_ADDR   ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 1                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.GET_STATUS_LEN    ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 1                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.GET_STATUS_ENDW   ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 1                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.GET_STATUS_WACK   ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 1                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.GET_STATUS_ACK_OK ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 1                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_CFG_STARTW    ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 1                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_CFG_CMD       ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 1                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_CFG_ADDR      ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 1                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_CFG_LEN       ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 1                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_CFG_DATA0     ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 1                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_CFG_DATA1     ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 1                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_CFG_FETCH     ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 1                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_CFG_ENDW      ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 1                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_CFG_WACK      ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 1                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_CFG_ACK_OK    ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 1                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.APPLY_CFG_STARTW  ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 1                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.APPLY_CFG_CMD     ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 1                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.APPLY_CFG_LEN     ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 1                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.APPLY_CFG_DATA0   ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 1                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.APPLY_CFG_DATA1   ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 1                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.APPLY_CFG_ENDW    ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 1                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.APPLY_CFG_WACK    ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 1                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.APPLY_CFG_ACK_OK  ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 1                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.REQ_ACK           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 1                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.REQ_ERROR         ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 1                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_ACQ_STARTW    ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 1                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_ACQ_CMD       ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 1                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_ACQ_ADDR      ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 1                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_ACQ_LEN       ; 0                         ; 0                       ; 0                       ; 0                        ; 0                       ; 1                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_ACQ_DATA      ; 0                         ; 0                       ; 0                       ; 0                        ; 1                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_ACQ_DATA1     ; 0                         ; 0                       ; 0                       ; 1                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_ACQ_ENDW      ; 0                         ; 0                       ; 1                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_ACQ_WACK      ; 0                         ; 1                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
; s_tx_state.SET_ACQ_ACK_OK    ; 1                         ; 0                       ; 0                       ; 0                        ; 0                       ; 0                      ; 0                       ; 0                      ; 0                         ; 0                    ; 0                  ; 0                           ; 0                         ; 0                         ; 0                          ; 0                          ; 0                        ; 0                        ; 0                           ; 0                         ; 0                       ; 0                       ; 0                        ; 0                        ; 0                        ; 0                      ; 0                       ; 0                      ; 0                         ; 0                            ; 0                          ; 0                          ; 0                         ; 0                          ; 0                         ; 0                            ; 1               ;
+------------------------------+---------------------------+-------------------------+-------------------------+--------------------------+-------------------------+------------------------+-------------------------+------------------------+---------------------------+----------------------+--------------------+-----------------------------+---------------------------+---------------------------+----------------------------+----------------------------+--------------------------+--------------------------+-----------------------------+---------------------------+-------------------------+-------------------------+--------------------------+--------------------------+--------------------------+------------------------+-------------------------+------------------------+---------------------------+------------------------------+----------------------------+----------------------------+---------------------------+----------------------------+---------------------------+------------------------------+-----------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|fee_controller:C_FEECONTROLLER|s_rx_state                                                                                                                                                                                                             ;
+-------------------------+-------------------------+-------------------------+-------------------------+-----------------------+-----------------------+-----------------------+---------------------+--------------------+----------------+----------------------+-----------------+
; Name                    ; s_rx_state.LATCH_STATUS ; s_rx_state.SHIFT_STATUS ; s_rx_state.FETCH_STATUS ; s_rx_state.WRITE_DATA ; s_rx_state.SHIFT_DATA ; s_rx_state.FETCH_DATA ; s_rx_state.GOT_NACK ; s_rx_state.GOT_ACK ; s_rx_state.CMD ; s_rx_state.FETCH_CMD ; s_rx_state.IDLE ;
+-------------------------+-------------------------+-------------------------+-------------------------+-----------------------+-----------------------+-----------------------+---------------------+--------------------+----------------+----------------------+-----------------+
; s_rx_state.IDLE         ; 0                       ; 0                       ; 0                       ; 0                     ; 0                     ; 0                     ; 0                   ; 0                  ; 0              ; 0                    ; 0               ;
; s_rx_state.FETCH_CMD    ; 0                       ; 0                       ; 0                       ; 0                     ; 0                     ; 0                     ; 0                   ; 0                  ; 0              ; 1                    ; 1               ;
; s_rx_state.CMD          ; 0                       ; 0                       ; 0                       ; 0                     ; 0                     ; 0                     ; 0                   ; 0                  ; 1              ; 0                    ; 1               ;
; s_rx_state.GOT_ACK      ; 0                       ; 0                       ; 0                       ; 0                     ; 0                     ; 0                     ; 0                   ; 1                  ; 0              ; 0                    ; 1               ;
; s_rx_state.GOT_NACK     ; 0                       ; 0                       ; 0                       ; 0                     ; 0                     ; 0                     ; 1                   ; 0                  ; 0              ; 0                    ; 1               ;
; s_rx_state.FETCH_DATA   ; 0                       ; 0                       ; 0                       ; 0                     ; 0                     ; 1                     ; 0                   ; 0                  ; 0              ; 0                    ; 1               ;
; s_rx_state.SHIFT_DATA   ; 0                       ; 0                       ; 0                       ; 0                     ; 1                     ; 0                     ; 0                   ; 0                  ; 0              ; 0                    ; 1               ;
; s_rx_state.WRITE_DATA   ; 0                       ; 0                       ; 0                       ; 1                     ; 0                     ; 0                     ; 0                   ; 0                  ; 0              ; 0                    ; 1               ;
; s_rx_state.FETCH_STATUS ; 0                       ; 0                       ; 1                       ; 0                     ; 0                     ; 0                     ; 0                   ; 0                  ; 0              ; 0                    ; 1               ;
; s_rx_state.SHIFT_STATUS ; 0                       ; 1                       ; 0                       ; 0                     ; 0                     ; 0                     ; 0                   ; 0                  ; 0              ; 0                    ; 1               ;
; s_rx_state.LATCH_STATUS ; 1                       ; 0                       ; 0                       ; 0                     ; 0                     ; 0                     ; 0                   ; 0                  ; 0              ; 0                    ; 1               ;
+-------------------------+-------------------------+-------------------------+-------------------------+-----------------------+-----------------------+-----------------------+---------------------+--------------------+----------------+----------------------+-----------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|USER_GET_CONFIG_RANGE_RD:C_PEDESTALS_USER_GET|sl_int_state               ;
+---------------------+------------------+--------------------+---------------------+-------------------+
; Name                ; sl_int_state.ACK ; sl_int_state.LATCH ; sl_int_state.REG_RD ; sl_int_state.IDLE ;
+---------------------+------------------+--------------------+---------------------+-------------------+
; sl_int_state.IDLE   ; 0                ; 0                  ; 0                   ; 0                 ;
; sl_int_state.REG_RD ; 0                ; 0                  ; 1                   ; 1                 ;
; sl_int_state.LATCH  ; 0                ; 1                  ; 0                   ; 1                 ;
; sl_int_state.ACK    ; 1                ; 0                  ; 0                   ; 1                 ;
+---------------------+------------------+--------------------+---------------------+-------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|USER_GET_CONFIG_RANGE_RD:C_HOUSEKEEPING_USER_GET|sl_int_state            ;
+---------------------+------------------+--------------------+---------------------+-------------------+
; Name                ; sl_int_state.ACK ; sl_int_state.LATCH ; sl_int_state.REG_RD ; sl_int_state.IDLE ;
+---------------------+------------------+--------------------+---------------------+-------------------+
; sl_int_state.IDLE   ; 0                ; 0                  ; 0                   ; 0                 ;
; sl_int_state.REG_RD ; 0                ; 0                  ; 1                   ; 1                 ;
; sl_int_state.LATCH  ; 0                ; 1                  ; 0                   ; 1                 ;
; sl_int_state.ACK    ; 1                ; 0                  ; 0                   ; 1                 ;
+---------------------+------------------+--------------------+---------------------+-------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|sl_int_state ;
+-------------------------+------------------------+----------------------+----------------------+-----------------------------------------------------------------------+
; Name                    ; sl_int_state.WAIT_STOP ; sl_int_state.DATA_AV ; sl_int_state.RECEIVE ; sl_int_state.WAIT_START                                               ;
+-------------------------+------------------------+----------------------+----------------------+-----------------------------------------------------------------------+
; sl_int_state.WAIT_START ; 0                      ; 0                    ; 0                    ; 0                                                                     ;
; sl_int_state.RECEIVE    ; 0                      ; 0                    ; 1                    ; 1                                                                     ;
; sl_int_state.DATA_AV    ; 0                      ; 1                    ; 0                    ; 1                                                                     ;
; sl_int_state.WAIT_STOP  ; 1                      ; 0                    ; 0                    ; 1                                                                     ;
+-------------------------+------------------------+----------------------+----------------------+-----------------------------------------------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER|sl_int_state ;
+-------------------------+-------------------+---------------------+-----------------------+--------------------+--------------------+------------------------------+
; Name                    ; sl_int_state.STOP ; sl_int_state.PARITY ; sl_int_state.TRANSMIT ; sl_int_state.START ; sl_int_state.LATCH ; sl_int_state.WAIT_START      ;
+-------------------------+-------------------+---------------------+-----------------------+--------------------+--------------------+------------------------------+
; sl_int_state.WAIT_START ; 0                 ; 0                   ; 0                     ; 0                  ; 0                  ; 0                            ;
; sl_int_state.LATCH      ; 0                 ; 0                   ; 0                     ; 0                  ; 1                  ; 1                            ;
; sl_int_state.START      ; 0                 ; 0                   ; 0                     ; 1                  ; 0                  ; 1                            ;
; sl_int_state.TRANSMIT   ; 0                 ; 0                   ; 1                     ; 0                  ; 0                  ; 1                            ;
; sl_int_state.PARITY     ; 0                 ; 1                   ; 0                     ; 0                  ; 0                  ; 1                            ;
; sl_int_state.STOP       ; 1                 ; 0                   ; 0                     ; 0                  ; 0                  ; 1                            ;
+-------------------------+-------------------+---------------------+-----------------------+--------------------+--------------------+------------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_timeout_state            ;
+------------------------------+------------------------------+----------------------------+----------------------------+
; Name                         ; sl_int_timeout_state.TIMEOUT ; sl_int_timeout_state.COUNT ; sl_int_timeout_state.RESET ;
+------------------------------+------------------------------+----------------------------+----------------------------+
; sl_int_timeout_state.RESET   ; 0                            ; 0                          ; 0                          ;
; sl_int_timeout_state.COUNT   ; 0                            ; 1                          ; 1                          ;
; sl_int_timeout_state.TIMEOUT ; 1                            ; 0                          ; 1                          ;
+------------------------------+------------------------------+----------------------------+----------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_process_state                                                                                                                                                                                                                                                                        ;
+-----------------------------------------+--------------------------+---------------------------------------+-----------------------------------+---------------------------------------+-----------------------------------+-----------------------------------------+----------------------------------------+---------------------------------------+---------------------------+
; Name                                    ; sl_int_process_state.ACK ; sl_int_process_state.SET_USER_SET_CMD ; sl_int_process_state.SET_USER_SET ; sl_int_process_state.APPLY_CONFIG_END ; sl_int_process_state.APPLY_CONFIG ; sl_int_process_state.APPLY_CONFIG_START ; sl_int_process_state.SET_READOUT_PARAM ; sl_int_process_state.SET_DIRECT_PARAM ; sl_int_process_state.IDLE ;
+-----------------------------------------+--------------------------+---------------------------------------+-----------------------------------+---------------------------------------+-----------------------------------+-----------------------------------------+----------------------------------------+---------------------------------------+---------------------------+
; sl_int_process_state.IDLE               ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 0                         ;
; sl_int_process_state.SET_DIRECT_PARAM   ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 1                                     ; 1                         ;
; sl_int_process_state.SET_READOUT_PARAM  ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 1                                      ; 0                                     ; 1                         ;
; sl_int_process_state.APPLY_CONFIG_START ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 1                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.APPLY_CONFIG       ; 0                        ; 0                                     ; 0                                 ; 0                                     ; 1                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.APPLY_CONFIG_END   ; 0                        ; 0                                     ; 0                                 ; 1                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.SET_USER_SET       ; 0                        ; 0                                     ; 1                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.SET_USER_SET_CMD   ; 0                        ; 1                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
; sl_int_process_state.ACK                ; 1                        ; 0                                     ; 0                                 ; 0                                     ; 0                                 ; 0                                       ; 0                                      ; 0                                     ; 1                         ;
+-----------------------------------------+--------------------------+---------------------------------------+-----------------------------------+---------------------------------------+-----------------------------------+-----------------------------------------+----------------------------------------+---------------------------------------+---------------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------------+-------------------------------------+-------------------------------+--------------------------------------+-----------------------------------------------+--------------------------+-------------------------+--------------------------------------+------------------------+--------------------------------------+---------------------------------------+-----------------------------------------+-----------------------------------------+-----------------------------------+-----------------------------------+-------------------------------------+-------------------------------+-------------------------------+-------------------------+-------------------------+--------------------------------+-----------------+-------------------+
; Name                                          ; sl_int_state.CMD_2FRM_PROCESS_DELAY ; sl_int_state.CMD_DECODE_DELAY ; sl_int_state.CMD_NOT_ADRRESSED_DELAY ; sl_int_state.CMD_SET_CONFIG_CMD_PROCESS_DELAY ; sl_int_state.CHECK_VALID ; sl_int_state.CMD_ANSWER ; sl_int_state.WAIT_FIFO_PROCESS_DELAY ; sl_int_state.WAIT_FIFO ; sl_int_state.CMD_SET_CONFIG_WAIT_CRC ; sl_int_state.CMD_SET_CONFIG_START_CRC ; sl_int_state.CMD_SET_CONFIG_ARG_PROCESS ; sl_int_state.CMD_SET_CONFIG_CMD_PROCESS ; sl_int_state.CMD_SET_CONFIG_VALID ; sl_int_state.CMD_2FRM_PROCESS_END ; sl_int_state.CMD_2FRM_PROCESS_CHECK ; sl_int_state.CMD_2FRM_PROCESS ; sl_int_state.CMD_1FRM_PROCESS ; sl_int_state.CMD_DECODE ; sl_int_state.ADD_DECODE ; sl_int_state.CMD_NOT_ADRRESSED ; sl_int_state.RD ; sl_int_state.IDLE ;
+-----------------------------------------------+-------------------------------------+-------------------------------+--------------------------------------+-----------------------------------------------+--------------------------+-------------------------+--------------------------------------+------------------------+--------------------------------------+---------------------------------------+-----------------------------------------+-----------------------------------------+-----------------------------------+-----------------------------------+-------------------------------------+-------------------------------+-------------------------------+-------------------------+-------------------------+--------------------------------+-----------------+-------------------+
; sl_int_state.IDLE                             ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 0                 ;
; sl_int_state.RD                               ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 1               ; 1                 ;
; sl_int_state.CMD_NOT_ADRRESSED                ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 1                              ; 0               ; 1                 ;
; sl_int_state.ADD_DECODE                       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 1                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_DECODE                       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 1                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_1FRM_PROCESS                 ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 1                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_2FRM_PROCESS                 ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 1                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_2FRM_PROCESS_CHECK           ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 1                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_2FRM_PROCESS_END             ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 1                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_VALID             ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 1                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_CMD_PROCESS       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 1                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_ARG_PROCESS       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 1                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_START_CRC         ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 1                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_WAIT_CRC          ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 1                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.WAIT_FIFO                        ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 1                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.WAIT_FIFO_PROCESS_DELAY          ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 1                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_ANSWER                       ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 1                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CHECK_VALID                      ; 0                                   ; 0                             ; 0                                    ; 0                                             ; 1                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_SET_CONFIG_CMD_PROCESS_DELAY ; 0                                   ; 0                             ; 0                                    ; 1                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_NOT_ADRRESSED_DELAY          ; 0                                   ; 0                             ; 1                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_DECODE_DELAY                 ; 0                                   ; 1                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
; sl_int_state.CMD_2FRM_PROCESS_DELAY           ; 1                                   ; 0                             ; 0                                    ; 0                                             ; 0                        ; 0                       ; 0                                    ; 0                      ; 0                                    ; 0                                     ; 0                                       ; 0                                       ; 0                                 ; 0                                 ; 0                                   ; 0                             ; 0                             ; 0                       ; 0                       ; 0                              ; 0               ; 1                 ;
+-----------------------------------------------+-------------------------------------+-------------------------------+--------------------------------------+-----------------------------------------------+--------------------------+-------------------------+--------------------------------------+------------------------+--------------------------------------+---------------------------------------+-----------------------------------------+-----------------------------------------+-----------------------------------+-----------------------------------+-------------------------------------+-------------------------------+-------------------------------+-------------------------+-------------------------+--------------------------------+-----------------+-------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_timeout_state       ;
+------------------------------+------------------------------+----------------------------+----------------------------+
; Name                         ; sl_int_timeout_state.TIMEOUT ; sl_int_timeout_state.COUNT ; sl_int_timeout_state.RESET ;
+------------------------------+------------------------------+----------------------------+----------------------------+
; sl_int_timeout_state.RESET   ; 0                            ; 0                          ; 0                          ;
; sl_int_timeout_state.COUNT   ; 0                            ; 1                          ; 1                          ;
; sl_int_timeout_state.TIMEOUT ; 1                            ; 0                          ; 1                          ;
+------------------------------+------------------------------+----------------------------+----------------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+----------------------------------------------+----------------------------------------------+-----------------------------------+-----------------------+------------------+-----------------+--------------------------------+-------------------------------+---------------------+-----------------------------+----------------------------------------+----------------------------------+-----------------------------------+-----------------------------+---------------------------+--------------------------+-------------------------+-------------------+
; Name                                         ; sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY ; sl_int_state.GET_CONFIG_CMD_DELAY ; sl_int_state.WR_DELAY ; sl_int_state.ACK ; sl_int_state.WR ; sl_int_state.GET_USER_CMD_WAIT ; sl_int_state.GET_USER_CMD_REQ ; sl_int_state.ANSWER ; sl_int_state.GET_CONFIG_END ; sl_int_state.GET_CONFIG_ARG_CHECK_FIFO ; sl_int_state.GET_CONFIG_WAIT_CRC ; sl_int_state.GET_CONFIG_START_CRC ; sl_int_state.GET_CONFIG_CMD ; sl_int_state.GET_BOARD_ID ; sl_int_state.READ_STATUS ; sl_int_state.FW_VERSION ; sl_int_state.IDLE ;
+----------------------------------------------+----------------------------------------------+-----------------------------------+-----------------------+------------------+-----------------+--------------------------------+-------------------------------+---------------------+-----------------------------+----------------------------------------+----------------------------------+-----------------------------------+-----------------------------+---------------------------+--------------------------+-------------------------+-------------------+
; sl_int_state.IDLE                            ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                             ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 0                 ;
; sl_int_state.FW_VERSION                      ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                             ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 1                       ; 1                 ;
; sl_int_state.READ_STATUS                     ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                             ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 1                        ; 0                       ; 1                 ;
; sl_int_state.GET_BOARD_ID                    ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                             ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 1                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_CMD                  ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                             ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 1                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_START_CRC            ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                             ; 0                   ; 0                           ; 0                                      ; 0                                ; 1                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_WAIT_CRC             ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                             ; 0                   ; 0                           ; 0                                      ; 1                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_ARG_CHECK_FIFO       ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                             ; 0                   ; 0                           ; 1                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_END                  ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                             ; 0                   ; 1                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.ANSWER                          ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                             ; 1                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_USER_CMD_REQ                ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 1                             ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_USER_CMD_WAIT               ; 0                                            ; 0                                 ; 0                     ; 0                ; 0               ; 1                              ; 0                             ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.WR                              ; 0                                            ; 0                                 ; 0                     ; 0                ; 1               ; 0                              ; 0                             ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.ACK                             ; 0                                            ; 0                                 ; 0                     ; 1                ; 0               ; 0                              ; 0                             ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.WR_DELAY                        ; 0                                            ; 0                                 ; 1                     ; 0                ; 0               ; 0                              ; 0                             ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_CMD_DELAY            ; 0                                            ; 1                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                             ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
; sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY ; 1                                            ; 0                                 ; 0                     ; 0                ; 0               ; 0                              ; 0                             ; 0                   ; 0                           ; 0                                      ; 0                                ; 0                                 ; 0                           ; 0                         ; 0                        ; 0                       ; 1                 ;
+----------------------------------------------+----------------------------------------------+-----------------------------------+-----------------------+------------------+-----------------+--------------------------------+-------------------------------+---------------------+-----------------------------+----------------------------------------+----------------------------------+-----------------------------------+-----------------------------+---------------------------+--------------------------+-------------------------+-------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_state ;
+-------------------------+---------------------+----------------------+--------------------------------------------------------+
; Name                    ; sl_int_state.CRC_AV ; sl_int_state.COMPUTE ; sl_int_state.WAIT_START                                ;
+-------------------------+---------------------+----------------------+--------------------------------------------------------+
; sl_int_state.WAIT_START ; 0                   ; 0                    ; 0                                                      ;
; sl_int_state.COMPUTE    ; 0                   ; 1                    ; 1                                                      ;
; sl_int_state.CRC_AV     ; 1                   ; 0                    ; 1                                                      ;
+-------------------------+---------------------+----------------------+--------------------------------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_state                                                            ;
+---------------------------+---------------------------+------------------------+------------------+-----------------+-------------------+--------------------+
; Name                      ; sl_int_state.WAIT_UC_FULL ; sl_int_state.CHECK_ZLP ; sl_int_state.ZLP ; sl_int_state.WR ; sl_int_state.IDLE ; sl_int_state.START ;
+---------------------------+---------------------------+------------------------+------------------+-----------------+-------------------+--------------------+
; sl_int_state.START        ; 0                         ; 0                      ; 0                ; 0               ; 0                 ; 0                  ;
; sl_int_state.IDLE         ; 0                         ; 0                      ; 0                ; 0               ; 1                 ; 1                  ;
; sl_int_state.WR           ; 0                         ; 0                      ; 0                ; 1               ; 0                 ; 1                  ;
; sl_int_state.ZLP          ; 0                         ; 0                      ; 1                ; 0               ; 0                 ; 1                  ;
; sl_int_state.CHECK_ZLP    ; 0                         ; 1                      ; 0                ; 0               ; 0                 ; 1                  ;
; sl_int_state.WAIT_UC_FULL ; 1                         ; 0                      ; 0                ; 0               ; 0                 ; 1                  ;
+---------------------------+---------------------------+------------------------+------------------+-----------------+-------------------+--------------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_start_state                                                                                            ;
+----------------------------+----------------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------------+
; Name                       ; sl_int_start_state.STARTED ; sl_int_start_state.START4 ; sl_int_start_state.START3 ; sl_int_start_state.START2 ; sl_int_start_state.START1 ; sl_int_start_state.START ;
+----------------------------+----------------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------------+
; sl_int_start_state.START   ; 0                          ; 0                         ; 0                         ; 0                         ; 0                         ; 0                        ;
; sl_int_start_state.START1  ; 0                          ; 0                         ; 0                         ; 0                         ; 1                         ; 1                        ;
; sl_int_start_state.START2  ; 0                          ; 0                         ; 0                         ; 1                         ; 0                         ; 1                        ;
; sl_int_start_state.START3  ; 0                          ; 0                         ; 1                         ; 0                         ; 0                         ; 1                        ;
; sl_int_start_state.START4  ; 0                          ; 1                         ; 0                         ; 0                         ; 0                         ; 1                        ;
; sl_int_start_state.STARTED ; 1                          ; 0                         ; 0                         ; 0                         ; 0                         ; 1                        ;
+----------------------------+----------------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis                                                                                                                                                                                                                                                                                                                                            ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name                                                                                                                                                                                                                                               ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe11a[10]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe11a[8]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe11a[9]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe11a[6]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe11a[7]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe11a[4]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe11a[5]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe11a[2]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe11a[3]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe11a[0]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe11a[1]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe10|dffe12a[4]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe10|dffe12a[2]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe10|dffe12a[3]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe10|dffe12a[0]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe10|dffe12a[1]                                                                                                                       ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe18a[10]                                                                                                                        ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe18a[8]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe18a[9]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe18a[6]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe18a[7]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe18a[4]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe18a[5]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe18a[2]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe18a[3]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe18a[0]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe18a[1]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe10a[10]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe10a[8]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe10a[9]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe10a[6]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe10a[7]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe10a[4]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe10a[5]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe10a[2]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe10a[3]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe10a[0]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9|dffe10a[1]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe10|dffe11a[4]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe10|dffe11a[2]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe10|dffe11a[3]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe10|dffe11a[0]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe10|dffe11a[1]                                                                                                                       ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe17a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe17a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe17a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe17a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe17a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe17a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe17a[1] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe14a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe14a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe14a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe14a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe14a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe14a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe14a[1] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe15a[6]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe15a[4]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe15a[5]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe15a[2]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe15a[3]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe15a[0]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe15a[1]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe18a[6]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe18a[4]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe18a[5]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe18a[2]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe18a[3]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe18a[0]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe18a[1]                                                                          ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe17a[10]                                                                                                                        ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe17a[8]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe17a[9]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe17a[6]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe17a[7]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe17a[4]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe17a[5]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe17a[2]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe17a[3]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe17a[0]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16|dffe17a[1]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_jd9:dffpipe13|dffe15a[4]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_jd9:dffpipe13|dffe15a[2]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_jd9:dffpipe13|dffe15a[3]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_jd9:dffpipe13|dffe15a[0]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_jd9:dffpipe13|dffe15a[1]                                                                                                                       ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe16a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe16a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe16a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe16a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe16a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe16a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15|dffe16a[1] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a[1] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe14a[6]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe14a[4]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe14a[5]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe14a[2]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe14a[3]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe14a[0]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13|dffe14a[1]                                                                          ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe15a[10]                                                                                                                        ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe15a[8]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe15a[9]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe15a[6]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe15a[7]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe15a[4]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe15a[5]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe15a[2]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe15a[3]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe15a[0]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe15a[1]                                                                                                                         ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe17a[6]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe17a[4]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe17a[5]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe17a[2]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe17a[3]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe17a[0]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16|dffe17a[1]                                                                          ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe14a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe14a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe14a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe14a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe14a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe14a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe14a[1] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe18a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe18a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe18a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe18a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe18a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe18a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe18a[1] ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe8a[10]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe8a[8]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe8a[9]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe8a[6]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe8a[7]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe8a[4]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe8a[5]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe8a[2]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe8a[3]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe8a[0]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe8a[1]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_jd9:dffpipe13|dffe14a[4]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_jd9:dffpipe13|dffe14a[2]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_jd9:dffpipe13|dffe14a[3]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_jd9:dffpipe13|dffe14a[0]                                                                                                                       ; yes                                                              ; yes                                        ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_jd9:dffpipe13|dffe14a[1]                                                                                                                       ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe14a[10]                                                                                                                        ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe14a[8]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe14a[9]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe14a[6]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe14a[7]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe14a[4]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe14a[5]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe14a[2]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe14a[3]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe14a[0]                                                                                                                         ; yes                                                              ; yes                                        ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13|dffe14a[1]                                                                                                                         ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe13a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe13a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe13a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe13a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe13a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe13a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12|dffe13a[1] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe17a[6] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe17a[4] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe17a[5] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe17a[2] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe17a[3] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe17a[0] ; yes                                                              ; yes                                        ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16|dffe17a[1] ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe7a[10]                                                                                                                        ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe7a[8]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe7a[9]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe7a[6]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe7a[7]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe7a[4]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe7a[5]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe7a[2]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe7a[3]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe7a[0]                                                                                                                         ; yes                                                              ; yes                                        ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6|dffe7a[1]                                                                                                                         ; yes                                                              ; yes                                        ;
; Total number of protected registers is 192                                                                                                                                                                                                                  ;                                                                  ;                                            ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                                     ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                                                                 ; Reason for Removal                                                                                                     ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+
; fee_controller:C_FEECONTROLLER|s_data_len[8]                                                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_word_id[2]                                                                                                                                               ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[30]                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_counter[0,1]                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_bwp|dffe15a[6] ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_brp|dffe15a[6] ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_bwp|dffe12a[6]                                                                          ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_brp|dffe12a[6]                                                                          ; Lost fanout                                                                                                            ;
; s_get_status_len[0..3,5,6]                                                                                                                                                                                                    ; Merged with s_get_status_len[7]                                                                                        ;
; fee_controller:C_FEECONTROLLER|s_data_len[1..3,7]                                                                                                                                                                             ; Merged with fee_controller:C_FEECONTROLLER|s_base_addr[2]                                                              ;
; fee_controller:C_FEECONTROLLER|s_data_len[5]                                                                                                                                                                                  ; Merged with fee_controller:C_FEECONTROLLER|s_data_len[6]                                                               ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_cmd_process_error[8..10]                                                                                                                                      ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_cmd_process_error[11]                      ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[26,27]                                                                                                                                       ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[25]                       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[9,11]                                                                                                                                                ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[10]                               ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_error[15]                                                                                                                                                ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_error[12]                             ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_error[15]                                                                                                                                                     ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_error[12]                                  ;
; s_get_status_len[8]                                                                                                                                                                                                           ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_error[2]                                                                                                                                                      ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_cmd_process_error[11]                                                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_error[2]                                                                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|ser_data_5_bits_filter:C_FILTER_SIN|sl_int_add[0]                                                ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[10]                                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_error[12]                                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                 ;
; serdes:SERDES|serializer:SERIAL_TX|s_data_10b[0]                                                                                                                                                                              ; Stuck at VCC due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[25]                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_error[12]                                                                                                                                                ; Stuck at GND due to stuck port data_in                                                                                 ;
; fee_controller:C_FEECONTROLLER|s_tx_state.GET_STATUS_ADDR                                                                                                                                                                     ; Lost fanout                                                                                                            ;
; fee_controller:C_FEECONTROLLER|s_tx_state.SET_CFG_ADDR                                                                                                                                                                        ; Lost fanout                                                                                                            ;
; fee_controller:C_FEECONTROLLER|s_tx_state.SET_ACQ_ADDR                                                                                                                                                                        ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_DECODE_DELAY                                                                                                                                        ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_2FRM_PROCESS_DELAY               ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_NOT_ADRRESSED_DELAY                                                                                                                                 ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_2FRM_PROCESS_DELAY               ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_SET_CONFIG_CMD_PROCESS_DELAY                                                                                                                        ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_2FRM_PROCESS_DELAY               ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.WAIT_FIFO_PROCESS_DELAY                                                                                                                                 ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_2FRM_PROCESS_DELAY               ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state.GET_CONFIG_CMD_DELAY                                                                                                                               ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state.WR_DELAY                                                                                                                                           ; Merged with UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_2FRM_PROCESS_DELAY                                                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                 ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_RX_fifo_rd_cnt[0,1]                                                                                                                                           ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_wr_cnt[0,1]                                                                                                                                      ; Lost fanout                                                                                                            ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_state.CMD_NOT_ADRRESSED                                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                 ;
; Total Number of Removed Registers = 55                                                                                                                                                                                        ;                                                                                                                        ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                      ;
+------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------+
; Register name                                                                                              ; Reason for Removal        ; Registers Removed due to This Register                                                  ;
+------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------+
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_error[2]                                   ; Stuck at GND              ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_error[2],          ;
;                                                                                                            ; due to stuck port data_in ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_RX_fifo_rd_cnt[1],      ;
;                                                                                                            ;                           ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_RX_fifo_rd_cnt[0]       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_cmd_process_error[11]                      ; Stuck at GND              ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_error[12],              ;
;                                                                                                            ; due to stuck port data_in ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_error[12]          ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_state.GET_CONFIG_ARG_CHECK_FIFO_DELAY ; Stuck at GND              ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_wr_cnt[1], ;
;                                                                                                            ; due to stuck port data_in ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_wr_cnt[0]  ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_word_id[2]                            ; Stuck at GND              ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[30]    ;
;                                                                                                            ; due to stuck port data_in ;                                                                                         ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[10]                               ; Stuck at GND              ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_TX_fifo_din[25]    ;
;                                                                                                            ; due to stuck port data_in ;                                                                                         ;
+------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 5317  ;
; Number of registers using Synchronous Clear  ; 127   ;
; Number of registers using Synchronous Load   ; 59    ;
; Number of registers using Asynchronous Clear ; 5112  ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4543  ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                                                                                                                         ; Fan out ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; serdes:SERDES|serializer:SERIAL_TX|bit_out                                                                                                                                                                                                ; 2       ;
; serdes:SERDES|serializer:SERIAL_TX|encoder_4b5b:MSBCODER|dout[0]                                                                                                                                                                          ; 1       ;
; serdes:SERDES|serializer:SERIAL_TX|encoder_4b5b:LSBCODER|dout[0]                                                                                                                                                                          ; 1       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_wrn[1]                                                                                                                                                                     ; 1       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_pkendn                                                                                                                                                                     ; 1       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_startn[0]                                                                                                                                                                  ; 6       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_wrn[0]                                                                                                                                                                     ; 2       ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|a_graycounter_kdc:wrptr_g1p|counter8a0                                                                                                                          ; 8       ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|a_graycounter_bu6:rdptr_g1p|counter5a0                                                                                                                          ; 8       ;
; s_l0_fifo_clr                                                                                                                                                                                                                             ; 30      ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_du6:rdptr_g1p|counter5a0    ; 6       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_startn[1]                                                                                                                                                                  ; 1       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|sl_int_uc_full                                                                                                                                                                    ; 5       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_bg6:rdptr_g1p|counter5a0                                                                             ; 6       ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|a_graycounter_kdc:wrptr_g1p|counter8a0                                                                                                                            ; 9       ;
; serdes:SERDES|serializer:SERIAL_TX|encoder_4b5b:MSBCODER|dout[4]                                                                                                                                                                          ; 1       ;
; serdes:SERDES|serializer:SERIAL_TX|s_data_10b[9]                                                                                                                                                                                          ; 2       ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|a_graycounter_kdc:wrptr_g1p|parity9                                                                                                                             ; 6       ;
; serdes:SERDES|deserializer:SERIAL_RX|decoder_4b5b:MSBDECODE|dout[0]                                                                                                                                                                       ; 1       ;
; serdes:SERDES|deserializer:SERIAL_RX|decoder_4b5b:MSBDECODE|dout[1]                                                                                                                                                                       ; 1       ;
; serdes:SERDES|deserializer:SERIAL_RX|decoder_4b5b:MSBDECODE|dout[2]                                                                                                                                                                       ; 1       ;
; serdes:SERDES|deserializer:SERIAL_RX|decoder_4b5b:MSBDECODE|dout[3]                                                                                                                                                                       ; 1       ;
; serdes:SERDES|deserializer:SERIAL_RX|decoder_4b5b:LSBDECODE|dout[0]                                                                                                                                                                       ; 1       ;
; serdes:SERDES|deserializer:SERIAL_RX|decoder_4b5b:LSBDECODE|dout[1]                                                                                                                                                                       ; 1       ;
; serdes:SERDES|deserializer:SERIAL_RX|decoder_4b5b:LSBDECODE|dout[2]                                                                                                                                                                       ; 1       ;
; serdes:SERDES|deserializer:SERIAL_RX|decoder_4b5b:LSBDECODE|dout[3]                                                                                                                                                                       ; 1       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|cntr_osd:cntr_b|counter_reg_bit0          ; 2       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_du6:rdptr_g1p|parity6       ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_7ub:wrptr_g1p|counter8a0                                                                             ; 5       ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|a_graycounter_ov6:rdptr_g1p|counter5a0                                                                                                                            ; 14      ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_bg6:rdptr_g1p|parity6                                                                                ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|cntr_osd:cntr_b|counter_reg_bit0          ; 2       ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|a_graycounter_kdc:wrptr_g1p|parity9                                                                                                                               ; 2       ;
; serdes:SERDES|serializer:SERIAL_TX|encoder_4b5b:MSBCODER|dout[3]                                                                                                                                                                          ; 1       ;
; serdes:SERDES|serializer:SERIAL_TX|s_data_10b[8]                                                                                                                                                                                          ; 1       ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|a_graycounter_ov6:rdptr_g1p|counter5a0                                                                                                                          ; 10      ;
; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|a_graycounter_7cc:wrptr_g1p|counter7a0                                                                                                                          ; 7       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_7ub:wrptr_g1p|parity9                                                                                ; 3       ;
; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|a_graycounter_ov6:rdptr_g1p|parity6                                                                                                                               ; 9       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_9cc:wrptr_g1p|counter8a0    ; 5       ;
; serdes:SERDES|serializer:SERIAL_TX|encoder_4b5b:MSBCODER|dout[2]                                                                                                                                                                          ; 1       ;
; serdes:SERDES|serializer:SERIAL_TX|s_data_10b[7]                                                                                                                                                                                          ; 1       ;
; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|a_graycounter_ov6:rdptr_g1p|parity6                                                                                                                             ; 2       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_8cc:wrptr_g1p|sub_parity9a0 ; 1       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_9cc:wrptr_g1p|parity9       ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[0]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[8]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_cu6:rdptr_g1p|sub_parity6a0 ; 1       ;
; serdes:SERDES|serializer:SERIAL_TX|encoder_4b5b:MSBCODER|dout[1]                                                                                                                                                                          ; 1       ;
; serdes:SERDES|serializer:SERIAL_TX|s_data_10b[6]                                                                                                                                                                                          ; 1       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[15]                                                                                                                                        ; 4       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[12]                                                                                                                                        ; 4       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[13]                                                                                                                                        ; 4       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[14]                                                                                                                                        ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[9]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[10]                                                                                                                                        ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[11]                                                                                                                                        ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[6]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[7]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[1]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[2]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[3]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[4]                                                                                                                                         ; 3       ;
; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[5]                                                                                                                                         ; 3       ;
; serdes:SERDES|serializer:SERIAL_TX|s_data_10b[5]                                                                                                                                                                                          ; 1       ;
; serdes:SERDES|serializer:SERIAL_TX|encoder_4b5b:LSBCODER|dout[4]                                                                                                                                                                          ; 1       ;
; serdes:SERDES|serializer:SERIAL_TX|s_data_10b[4]                                                                                                                                                                                          ; 1       ;
; serdes:SERDES|serializer:SERIAL_TX|encoder_4b5b:LSBCODER|dout[3]                                                                                                                                                                          ; 1       ;
; serdes:SERDES|serializer:SERIAL_TX|s_data_10b[3]                                                                                                                                                                                          ; 1       ;
; serdes:SERDES|serializer:SERIAL_TX|encoder_4b5b:LSBCODER|dout[2]                                                                                                                                                                          ; 1       ;
; serdes:SERDES|serializer:SERIAL_TX|s_data_10b[2]                                                                                                                                                                                          ; 1       ;
; serdes:SERDES|serializer:SERIAL_TX|encoder_4b5b:LSBCODER|dout[1]                                                                                                                                                                          ; 1       ;
; serdes:SERDES|serializer:SERIAL_TX|s_data_10b[1]                                                                                                                                                                                          ; 1       ;
; Total number of inverted registers = 73                                                                                                                                                                                                   ;         ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_cmd_process_error[7]                                                          ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_counter[3]                                         ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER|sl_int_shift[4]      ;
; 3:1                ; 15 bits   ; 30 LEs        ; 0 LEs                ; 30 LEs                 ; Yes        ; |FEE_Control|fee_controller:C_FEECONTROLLER|s_timeout_cnt[9]                                                                                               ;
; 3:1                ; 8 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |FEE_Control|fee_controller:C_FEECONTROLLER|s_addr_cnt[3]                                                                                                  ;
; 3:1                ; 9 bits    ; 18 LEs        ; 0 LEs                ; 18 LEs                 ; Yes        ; |FEE_Control|fee_controller:C_FEECONTROLLER|s_rx_data_cnt[0]                                                                                               ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|sl_int_count[0]  ;
; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |FEE_Control|serdes:SERDES|serializer:SERIAL_TX|s_bit_cnt[0]                                                                                               ;
; 3:1                ; 10 bits   ; 20 LEs        ; 0 LEs                ; 20 LEs                 ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|sl_int_shift[10] ;
; 3:1                ; 21 bits   ; 42 LEs        ; 21 LEs               ; 21 LEs                 ; Yes        ; |FEE_Control|s_DATA_FIFO_din[21]                                                                                                                           ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_dpram_addr[8]                                                                 ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |FEE_Control|serdes:SERDES|deserializer:SERIAL_RX|bit_cnt[0]                                                                                               ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[6]                                                                   ;
; 5:1                ; 5 bits    ; 15 LEs        ; 10 LEs               ; 5 LEs                  ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d12[0]                                                                   ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |FEE_Control|USER_GET_CONFIG_RANGE_RD:C_HOUSEKEEPING_USER_GET|sl_int_data[0]                                                                               ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_sc_counter[0]                                                                 ;
; 6:1                ; 16 bits   ; 64 LEs        ; 0 LEs                ; 64 LEs                 ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_dpram_addr[6]                                                            ;
; 6:1                ; 2 bits    ; 8 LEs         ; 2 LEs                ; 6 LEs                  ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_dpram_addr[8]                                                            ;
; 7:1                ; 7 bits    ; 28 LEs        ; 7 LEs                ; 21 LEs                 ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|sl_int_frame_cnt[0]                                                                  ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |FEE_Control|USER_GET_CONFIG_RANGE_RD:C_HOUSEKEEPING_USER_GET|sl_int_data[12]                                                                              ;
; 9:1                ; 5 bits    ; 30 LEs        ; 25 LEs               ; 5 LEs                  ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d16[9]                                                                   ;
; 10:1               ; 3 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d16[6]                                                                   ;
; 10:1               ; 3 bits    ; 18 LEs        ; 21 LEs               ; -3 LEs                 ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d16[4]                                                                   ;
; 10:1               ; 3 bits    ; 18 LEs        ; 21 LEs               ; -3 LEs                 ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|sl_int_d16[12]                                                                  ;
; 125:1              ; 8 bits    ; 664 LEs       ; 664 LEs              ; 0 LEs                  ; Yes        ; |FEE_Control|USER_GET_CONFIG_RANGE_RD:C_PEDESTALS_USER_GET|sl_int_data[0]                                                                                  ;
; 122:1              ; 8 bits    ; 648 LEs       ; 648 LEs              ; 0 LEs                  ; Yes        ; |FEE_Control|USER_GET_CONFIG_RANGE_RD:C_PEDESTALS_USER_GET|sl_int_data[14]                                                                                 ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|sl_int_crc[0]                                             ;
; 5:1                ; 9 bits    ; 27 LEs        ; 18 LEs               ; 9 LEs                  ; Yes        ; |FEE_Control|serdes:SERDES|serializer:SERIAL_TX|s_data_10b[9]                                                                                              ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |FEE_Control|USER_GET_CONFIG_RANGE_RD:C_PEDESTALS_USER_GET|Mux11                                                                                           ;
; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |FEE_Control|USER_GET_CONFIG_RANGE_RD:C_HOUSEKEEPING_USER_GET|Mux8                                                                                         ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; No         ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|Selector17                                                ;
; 8:1                ; 4 bits    ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC|Mux1                                                      ;
; 7:1                ; 4 bits    ; 16 LEs        ; 12 LEs               ; 4 LEs                  ; No         ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|Selector1        ;
; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; No         ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|Selector12                                                                           ;
; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; No         ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|Selector10                                                                      ;
; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; No         ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER|Selector1            ;
; 9:1                ; 4 bits    ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; No         ; |FEE_Control|USER_GET_CONFIG_RANGE_RD:C_PEDESTALS_USER_GET|Selector2                                                                                       ;
; 9:1                ; 4 bits    ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; No         ; |FEE_Control|USER_GET_CONFIG_RANGE_RD:C_HOUSEKEEPING_USER_GET|Selector3                                                                                    ;
; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|Selector4                                                                             ;
; 12:1               ; 6 bits    ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; No         ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|Selector11                                                                            ;
; 11:1               ; 2 bits    ; 14 LEs        ; 6 LEs                ; 8 LEs                  ; No         ; |FEE_Control|fee_controller:C_FEECONTROLLER|Selector6                                                                                                      ;
; 13:1               ; 5 bits    ; 40 LEs        ; 30 LEs               ; 10 LEs                 ; No         ; |FEE_Control|Selector4                                                                                                                                     ;
; 11:1               ; 3 bits    ; 21 LEs        ; 15 LEs               ; 6 LEs                  ; No         ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|Selector82                                                                           ;
; 11:1               ; 4 bits    ; 28 LEs        ; 16 LEs               ; 12 LEs                 ; No         ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|Selector76                                                                           ;
; 44:1               ; 10 bits   ; 290 LEs       ; 100 LEs              ; 190 LEs                ; No         ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER|Selector28                                                                      ;
; 20:1               ; 7 bits    ; 91 LEs        ; 35 LEs               ; 56 LEs                 ; No         ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|Selector43                                                                           ;
; 50:1               ; 2 bits    ; 66 LEs        ; 22 LEs               ; 44 LEs                 ; No         ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|Selector35                                                                           ;
; 50:1               ; 2 bits    ; 66 LEs        ; 18 LEs               ; 48 LEs                 ; No         ; |FEE_Control|UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER|Selector38                                                                           ;
; 20:1               ; 7 bits    ; 91 LEs        ; 35 LEs               ; 56 LEs                 ; No         ; |FEE_Control|fee_controller:C_FEECONTROLLER|Selector23                                                                                                     ;
; 21:1               ; 2 bits    ; 28 LEs        ; 8 LEs                ; 20 LEs                 ; No         ; |FEE_Control|fee_controller:C_FEECONTROLLER|Selector38                                                                                                     ;
; 22:1               ; 2 bits    ; 28 LEs        ; 8 LEs                ; 20 LEs                 ; No         ; |FEE_Control|fee_controller:C_FEECONTROLLER|Selector28                                                                                                     ;
; 22:1               ; 2 bits    ; 28 LEs        ; 8 LEs                ; 20 LEs                 ; No         ; |FEE_Control|fee_controller:C_FEECONTROLLER|Selector31                                                                                                     ;
; 22:1               ; 2 bits    ; 28 LEs        ; 8 LEs                ; 20 LEs                 ; No         ; |FEE_Control|fee_controller:C_FEECONTROLLER|Selector49                                                                                                     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------+
; Source assignments for Top-level Entity: |FEE_Control     ;
+------------------------------+-------+------+-------------+
; Assignment                   ; Value ; From ; To          ;
+------------------------------+-------+------+-------------+
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; s_clk_main  ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; s_clk_main  ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; s_clk32     ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; s_clk32     ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; s_clk_sync  ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; s_clk_sync  ;
; IGNORE_LCELL_BUFFERS         ; off   ; -    ; s_usb_ready ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; s_usb_ready ;
+------------------------------+-------+------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component ;
+-------------------------+-------------+------+-----------------------------------------------------------------------------------------+
; Assignment              ; Value       ; From ; To                                                                                      ;
+-------------------------+-------------+------+-----------------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; -    ; -                                                                                       ;
; PRESERVE_REGISTER       ; ON          ; -    ; output_cell_L                                                                           ;
; DDIO_OUTPUT_REGISTER    ; LOW         ; -    ; output_cell_L                                                                           ;
; DDIO_OUTPUT_REGISTER    ; HIGH        ; -    ; mux                                                                                     ;
+-------------------------+-------------+------+-----------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated ;
+-----------------------------+---------+------+---------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                                                  ;
+-----------------------------+---------+------+---------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                                                   ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                                                   ;
+-----------------------------+---------+------+---------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                ;
+---------------------------------+-------+------+-------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                 ;
+---------------------------------+-------+------+-------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                     ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                      ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                      ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                      ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                                ;
+---------------------------------------+-------+------+----------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_bg6:rdptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                        ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                   ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_7ub:wrptr_g1p ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                        ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                   ;
+----------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|altsyncram_cia1:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                       ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                        ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:rs_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                              ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                               ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:rs_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                              ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                               ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                         ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                          ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                          ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                          ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                          ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                          ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_brp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                              ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                               ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:ws_bwp ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                              ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                               ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                         ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                          ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                          ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                          ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                          ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                          ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated ;
+---------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                                                              ;
+---------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                                                               ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                                                               ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                                                               ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                                                               ;
+---------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_cu6:rdptr_g1p ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                                                                 ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; sub_parity6a0                                                                                                                                                                                                      ;
; POWER_UP_LEVEL ; LOW   ; -    ; parity5                                                                                                                                                                                                            ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_9cc:wrptr_g1p ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                                                                 ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                                                                                                         ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                                                                                                            ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|altsyncram_po91:fifo_ram ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                 ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                  ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                                                                   ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                                                                   ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                                                                   ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                                                                   ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                                                                   ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                     ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                      ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_brp ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_bwp ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                       ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                        ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                  ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                                                                   ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                                                                   ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                                                                   ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                                                                   ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                                                                   ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                     ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                      ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|cntr_osd:cntr_b ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                                                     ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter_reg_bit0                                                                                                                                                                                       ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated ;
+---------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                            ; Value ; From ; To                                                                                                                                                              ;
+---------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                                                                                                               ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                                                                                                               ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                                                                                                               ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                                                                                                               ;
+---------------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_du6:rdptr_g1p ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                                                                 ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                                                                         ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                                                            ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_8cc:wrptr_g1p ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                                                                 ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; sub_parity9a0                                                                                                                                                                                                      ;
; POWER_UP_LEVEL ; LOW   ; -    ; parity8                                                                                                                                                                                                            ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|altsyncram_qo91:fifo_ram ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                 ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                  ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                                                                   ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                                                                   ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                                                                   ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                                                                   ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                                                                   ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                     ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                      ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                  ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                                                                   ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                                                                   ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                                                                                                                                                   ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                                                                                                                                                   ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                                                                                                                                                   ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                                                     ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                                                      ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|cntr_osd:cntr_b ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                                                                                                                                     ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter_reg_bit0                                                                                                                                                                                       ;
+----------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------+
; Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+--------------------+
; Assignment                      ; Value ; From ; To                 ;
+---------------------------------+-------+------+--------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                  ;
+---------------------------------+-------+------+--------------------+


+------------------------------------------------------------------------------------------------+
; Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated ;
+---------------------------------------+-------+------+-----------------------------------------+
; Assignment                            ; Value ; From ; To                                      ;
+---------------------------------------+-------+------+-----------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                       ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                       ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                       ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                       ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                 ;
+---------------------------------------+-------+------+-----------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|a_graycounter_ov6:rdptr_g1p ;
+----------------+-------+------+--------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                         ;
+----------------+-------+------+--------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                 ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                    ;
+----------------+-------+------+--------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|a_graycounter_kdc:wrptr_g1p ;
+----------------+-------+------+--------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                         ;
+----------------+-------+------+--------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                 ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                    ;
+----------------+-------+------+--------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|altsyncram_m8d1:fifo_ram ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                        ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                         ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|dffpipe_pe9:rs_brp ;
+---------------------------------+-------+------+------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                               ;
+---------------------------------+-------+------+------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                ;
+---------------------------------+-------+------+------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|dffpipe_pe9:rs_bwp ;
+---------------------------------+-------+------+------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                               ;
+---------------------------------+-------+------+------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                ;
+---------------------------------+-------+------+------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp ;
+-----------------------------+------------------------+------+-------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                          ;
+-----------------------------+------------------------+------+-------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                           ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                           ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                           ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                           ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                           ;
+-----------------------------+------------------------+------+-------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                             ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                              ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|dffpipe_pe9:ws_brp ;
+---------------------------------+-------+------+------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                               ;
+---------------------------------+-------+------+------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                ;
+---------------------------------+-------+------+------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|dffpipe_pe9:ws_bwp ;
+---------------------------------+-------+------+------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                               ;
+---------------------------------+-------+------+------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                ;
+---------------------------------+-------+------+------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp ;
+-----------------------------+------------------------+------+-------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                          ;
+-----------------------------+------------------------+------+-------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                           ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                           ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                           ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                           ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                           ;
+-----------------------------+------------------------+------+-------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                             ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                              ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Source assignments for UGB_CFG_DPRAM:C_DPRAM|altsyncram:altsyncram_component|altsyncram_s1v3:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------+
; Assignment                      ; Value              ; From ; To                                            ;
+---------------------------------+--------------------+------+-----------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                             ;
+---------------------------------+--------------------+------+-----------------------------------------------+


+-----------------------------------------------------------------------+
; Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+----------------------+
; Assignment                      ; Value ; From ; To                   ;
+---------------------------------+-------+------+----------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                    ;
+---------------------------------+-------+------+----------------------+


+--------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated ;
+---------------------------------------+-------+------+-------------------------------------------+
; Assignment                            ; Value ; From ; To                                        ;
+---------------------------------------+-------+------+-------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                         ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                         ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                         ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                         ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                   ;
+---------------------------------------+-------+------+-------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|a_graycounter_ov6:rdptr_g1p ;
+----------------+-------+------+----------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                           ;
+----------------+-------+------+----------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                   ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                      ;
+----------------+-------+------+----------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|a_graycounter_kdc:wrptr_g1p ;
+----------------+-------+------+----------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                           ;
+----------------+-------+------+----------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                   ;
; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                      ;
+----------------+-------+------+----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|altsyncram_s5d1:fifo_ram ;
+---------------------------------+--------------------+------+-------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                          ;
+---------------------------------+--------------------+------+-------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                           ;
+---------------------------------+--------------------+------+-------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp ;
+-----------------------------+------------------------+------+---------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                            ;
+-----------------------------+------------------------+------+---------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                             ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                             ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                             ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                             ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                             ;
+-----------------------------+------------------------+------+---------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6 ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp ;
+-----------------------------+------------------------+------+---------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                            ;
+-----------------------------+------------------------+------+---------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                             ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                             ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                             ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                             ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                             ;
+-----------------------------+------------------------+------+---------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9 ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                              ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                               ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------+
; Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+----------------------+
; Assignment                      ; Value ; From ; To                   ;
+---------------------------------+-------+------+----------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                    ;
+---------------------------------+-------+------+----------------------+


+--------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated ;
+---------------------------------------+-------+------+-------------------------------------------+
; Assignment                            ; Value ; From ; To                                        ;
+---------------------------------------+-------+------+-------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                         ;
; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                         ;
; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                         ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                         ;
; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                   ;
+---------------------------------------+-------+------+-------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|a_graycounter_bu6:rdptr_g1p ;
+----------------+-------+------+----------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                           ;
+----------------+-------+------+----------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                   ;
; POWER_UP_LEVEL ; LOW   ; -    ; parity6                                                                                      ;
+----------------+-------+------+----------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|a_graycounter_7cc:wrptr_g1p ;
+----------------+-------+------+----------------------------------------------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                                                           ;
+----------------+-------+------+----------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH  ; -    ; counter7a0                                                                                   ;
; POWER_UP_LEVEL ; LOW   ; -    ; parity8                                                                                      ;
+----------------+-------+------+----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|altsyncram_03d1:fifo_ram ;
+---------------------------------+--------------------+------+-------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                          ;
+---------------------------------+--------------------+------+-------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                           ;
+---------------------------------+--------------------+------+-------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp ;
+-----------------------------+------------------------+------+---------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                            ;
+-----------------------------+------------------------+------+---------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                             ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                             ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                             ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                             ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                             ;
+-----------------------------+------------------------+------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe10 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                               ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp ;
+-----------------------------+------------------------+------+---------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                            ;
+-----------------------------+------------------------+------+---------------------------------------------------------------+
; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                             ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                             ;
; PRESERVE_REGISTER           ; ON                     ; -    ; -                                                             ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; -                                                             ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; -                                                             ;
+-----------------------------+------------------------+------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_jd9:dffpipe13 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                               ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo|altsyncram_j0i1:FIFOram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                         ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                          ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: PLL_60:C_PLL|PLL_60_0002:pll_60_inst|altera_pll:altera_pll_i ;
+--------------------------------------+------------------------+-------------------------------------------+
; Parameter Name                       ; Value                  ; Type                                      ;
+--------------------------------------+------------------------+-------------------------------------------+
; reference_clock_frequency            ; 40.0 MHz               ; String                                    ;
; fractional_vco_multiplier            ; false                  ; String                                    ;
; pll_type                             ; General                ; String                                    ;
; pll_subtype                          ; General                ; String                                    ;
; number_of_clocks                     ; 4                      ; Signed Integer                            ;
; operation_mode                       ; direct                 ; String                                    ;
; deserialization_factor               ; 4                      ; Signed Integer                            ;
; data_rate                            ; 0                      ; Signed Integer                            ;
; sim_additional_refclk_cycles_to_lock ; 0                      ; Signed Integer                            ;
; output_clock_frequency0              ; 60.000000 MHz          ; String                                    ;
; phase_shift0                         ; 0 ps                   ; String                                    ;
; duty_cycle0                          ; 50                     ; Signed Integer                            ;
; output_clock_frequency1              ; 32.000000 MHz          ; String                                    ;
; phase_shift1                         ; 0 ps                   ; String                                    ;
; duty_cycle1                          ; 50                     ; Signed Integer                            ;
; output_clock_frequency2              ; 15.000000 MHz          ; String                                    ;
; phase_shift2                         ; 0 ps                   ; String                                    ;
; duty_cycle2                          ; 50                     ; Signed Integer                            ;
; output_clock_frequency3              ; 40.000000 MHz          ; String                                    ;
; phase_shift3                         ; 0 ps                   ; String                                    ;
; duty_cycle3                          ; 50                     ; Signed Integer                            ;
; output_clock_frequency4              ; 0 MHz                  ; String                                    ;
; phase_shift4                         ; 0 ps                   ; String                                    ;
; duty_cycle4                          ; 50                     ; Signed Integer                            ;
; output_clock_frequency5              ; 0 MHz                  ; String                                    ;
; phase_shift5                         ; 0 ps                   ; String                                    ;
; duty_cycle5                          ; 50                     ; Signed Integer                            ;
; output_clock_frequency6              ; 0 MHz                  ; String                                    ;
; phase_shift6                         ; 0 ps                   ; String                                    ;
; duty_cycle6                          ; 50                     ; Signed Integer                            ;
; output_clock_frequency7              ; 0 MHz                  ; String                                    ;
; phase_shift7                         ; 0 ps                   ; String                                    ;
; duty_cycle7                          ; 50                     ; Signed Integer                            ;
; output_clock_frequency8              ; 0 MHz                  ; String                                    ;
; phase_shift8                         ; 0 ps                   ; String                                    ;
; duty_cycle8                          ; 50                     ; Signed Integer                            ;
; output_clock_frequency9              ; 0 MHz                  ; String                                    ;
; phase_shift9                         ; 0 ps                   ; String                                    ;
; duty_cycle9                          ; 50                     ; Signed Integer                            ;
; output_clock_frequency10             ; 0 MHz                  ; String                                    ;
; phase_shift10                        ; 0 ps                   ; String                                    ;
; duty_cycle10                         ; 50                     ; Signed Integer                            ;
; output_clock_frequency11             ; 0 MHz                  ; String                                    ;
; phase_shift11                        ; 0 ps                   ; String                                    ;
; duty_cycle11                         ; 50                     ; Signed Integer                            ;
; output_clock_frequency12             ; 0 MHz                  ; String                                    ;
; phase_shift12                        ; 0 ps                   ; String                                    ;
; duty_cycle12                         ; 50                     ; Signed Integer                            ;
; output_clock_frequency13             ; 0 MHz                  ; String                                    ;
; phase_shift13                        ; 0 ps                   ; String                                    ;
; duty_cycle13                         ; 50                     ; Signed Integer                            ;
; output_clock_frequency14             ; 0 MHz                  ; String                                    ;
; phase_shift14                        ; 0 ps                   ; String                                    ;
; duty_cycle14                         ; 50                     ; Signed Integer                            ;
; output_clock_frequency15             ; 0 MHz                  ; String                                    ;
; phase_shift15                        ; 0 ps                   ; String                                    ;
; duty_cycle15                         ; 50                     ; Signed Integer                            ;
; output_clock_frequency16             ; 0 MHz                  ; String                                    ;
; phase_shift16                        ; 0 ps                   ; String                                    ;
; duty_cycle16                         ; 50                     ; Signed Integer                            ;
; output_clock_frequency17             ; 0 MHz                  ; String                                    ;
; phase_shift17                        ; 0 ps                   ; String                                    ;
; duty_cycle17                         ; 50                     ; Signed Integer                            ;
; clock_name_0                         ;                        ; String                                    ;
; clock_name_1                         ;                        ; String                                    ;
; clock_name_2                         ;                        ; String                                    ;
; clock_name_3                         ;                        ; String                                    ;
; clock_name_4                         ;                        ; String                                    ;
; clock_name_5                         ;                        ; String                                    ;
; clock_name_6                         ;                        ; String                                    ;
; clock_name_7                         ;                        ; String                                    ;
; clock_name_8                         ;                        ; String                                    ;
; clock_name_global_0                  ; false                  ; String                                    ;
; clock_name_global_1                  ; false                  ; String                                    ;
; clock_name_global_2                  ; false                  ; String                                    ;
; clock_name_global_3                  ; false                  ; String                                    ;
; clock_name_global_4                  ; false                  ; String                                    ;
; clock_name_global_5                  ; false                  ; String                                    ;
; clock_name_global_6                  ; false                  ; String                                    ;
; clock_name_global_7                  ; false                  ; String                                    ;
; clock_name_global_8                  ; false                  ; String                                    ;
; m_cnt_hi_div                         ; 1                      ; Signed Integer                            ;
; m_cnt_lo_div                         ; 1                      ; Signed Integer                            ;
; m_cnt_bypass_en                      ; false                  ; String                                    ;
; m_cnt_odd_div_duty_en                ; false                  ; String                                    ;
; n_cnt_hi_div                         ; 1                      ; Signed Integer                            ;
; n_cnt_lo_div                         ; 1                      ; Signed Integer                            ;
; n_cnt_bypass_en                      ; false                  ; String                                    ;
; n_cnt_odd_div_duty_en                ; false                  ; String                                    ;
; c_cnt_hi_div0                        ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div0                        ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en0                     ; false                  ; String                                    ;
; c_cnt_in_src0                        ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en0               ; false                  ; String                                    ;
; c_cnt_prst0                          ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst0                   ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div1                        ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div1                        ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en1                     ; false                  ; String                                    ;
; c_cnt_in_src1                        ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en1               ; false                  ; String                                    ;
; c_cnt_prst1                          ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst1                   ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div2                        ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div2                        ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en2                     ; false                  ; String                                    ;
; c_cnt_in_src2                        ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en2               ; false                  ; String                                    ;
; c_cnt_prst2                          ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst2                   ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div3                        ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div3                        ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en3                     ; false                  ; String                                    ;
; c_cnt_in_src3                        ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en3               ; false                  ; String                                    ;
; c_cnt_prst3                          ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst3                   ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div4                        ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div4                        ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en4                     ; false                  ; String                                    ;
; c_cnt_in_src4                        ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en4               ; false                  ; String                                    ;
; c_cnt_prst4                          ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst4                   ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div5                        ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div5                        ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en5                     ; false                  ; String                                    ;
; c_cnt_in_src5                        ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en5               ; false                  ; String                                    ;
; c_cnt_prst5                          ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst5                   ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div6                        ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div6                        ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en6                     ; false                  ; String                                    ;
; c_cnt_in_src6                        ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en6               ; false                  ; String                                    ;
; c_cnt_prst6                          ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst6                   ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div7                        ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div7                        ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en7                     ; false                  ; String                                    ;
; c_cnt_in_src7                        ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en7               ; false                  ; String                                    ;
; c_cnt_prst7                          ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst7                   ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div8                        ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div8                        ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en8                     ; false                  ; String                                    ;
; c_cnt_in_src8                        ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en8               ; false                  ; String                                    ;
; c_cnt_prst8                          ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst8                   ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div9                        ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div9                        ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en9                     ; false                  ; String                                    ;
; c_cnt_in_src9                        ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en9               ; false                  ; String                                    ;
; c_cnt_prst9                          ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst9                   ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div10                       ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div10                       ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en10                    ; false                  ; String                                    ;
; c_cnt_in_src10                       ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en10              ; false                  ; String                                    ;
; c_cnt_prst10                         ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst10                  ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div11                       ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div11                       ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en11                    ; false                  ; String                                    ;
; c_cnt_in_src11                       ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en11              ; false                  ; String                                    ;
; c_cnt_prst11                         ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst11                  ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div12                       ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div12                       ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en12                    ; false                  ; String                                    ;
; c_cnt_in_src12                       ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en12              ; false                  ; String                                    ;
; c_cnt_prst12                         ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst12                  ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div13                       ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div13                       ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en13                    ; false                  ; String                                    ;
; c_cnt_in_src13                       ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en13              ; false                  ; String                                    ;
; c_cnt_prst13                         ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst13                  ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div14                       ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div14                       ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en14                    ; false                  ; String                                    ;
; c_cnt_in_src14                       ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en14              ; false                  ; String                                    ;
; c_cnt_prst14                         ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst14                  ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div15                       ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div15                       ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en15                    ; false                  ; String                                    ;
; c_cnt_in_src15                       ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en15              ; false                  ; String                                    ;
; c_cnt_prst15                         ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst15                  ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div16                       ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div16                       ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en16                    ; false                  ; String                                    ;
; c_cnt_in_src16                       ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en16              ; false                  ; String                                    ;
; c_cnt_prst16                         ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst16                  ; 0                      ; Signed Integer                            ;
; c_cnt_hi_div17                       ; 1                      ; Signed Integer                            ;
; c_cnt_lo_div17                       ; 1                      ; Signed Integer                            ;
; c_cnt_bypass_en17                    ; false                  ; String                                    ;
; c_cnt_in_src17                       ; ph_mux_clk             ; String                                    ;
; c_cnt_odd_div_duty_en17              ; false                  ; String                                    ;
; c_cnt_prst17                         ; 1                      ; Signed Integer                            ;
; c_cnt_ph_mux_prst17                  ; 0                      ; Signed Integer                            ;
; pll_vco_div                          ; 1                      ; Signed Integer                            ;
; pll_slf_rst                          ; false                  ; String                                    ;
; pll_bw_sel                           ; low                    ; String                                    ;
; pll_output_clk_frequency             ; 0 MHz                  ; String                                    ;
; pll_cp_current                       ; 0                      ; Signed Integer                            ;
; pll_bwctrl                           ; 0                      ; Signed Integer                            ;
; pll_fractional_division              ; 1                      ; Signed Integer                            ;
; pll_fractional_cout                  ; 24                     ; Signed Integer                            ;
; pll_dsm_out_sel                      ; 1st_order              ; String                                    ;
; mimic_fbclk_type                     ; gclk                   ; String                                    ;
; pll_fbclk_mux_1                      ; glb                    ; String                                    ;
; pll_fbclk_mux_2                      ; fb_1                   ; String                                    ;
; pll_m_cnt_in_src                     ; ph_mux_clk             ; String                                    ;
; pll_vcoph_div                        ; 1                      ; Signed Integer                            ;
; refclk1_frequency                    ; 0 MHz                  ; String                                    ;
; pll_clkin_0_src                      ; clk_0                  ; String                                    ;
; pll_clkin_1_src                      ; clk_0                  ; String                                    ;
; pll_clk_loss_sw_en                   ; false                  ; String                                    ;
; pll_auto_clk_sw_en                   ; false                  ; String                                    ;
; pll_manu_clk_sw_en                   ; false                  ; String                                    ;
; pll_clk_sw_dly                       ; 0                      ; Signed Integer                            ;
; pll_extclk_0_cnt_src                 ; pll_extclk_cnt_src_vss ; String                                    ;
; pll_extclk_1_cnt_src                 ; pll_extclk_cnt_src_vss ; String                                    ;
+--------------------------------------+------------------------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB ;
+-----------------------------+-------+-------------------------------------------+
; Parameter Name              ; Value ; Type                                      ;
+-----------------------------+-------+-------------------------------------------+
; x_reset_active              ; '0'   ; Enumerated                                ;
; x_nb_config_word16          ; 256   ; Signed Integer                            ;
; x_nb_config_word16_size     ; 8     ; Signed Integer                            ;
; x_nb_dpram_size             ; 10    ; Signed Integer                            ;
; x_nb_devices_size           ; 2     ; Signed Integer                            ;
; x_uc_data_size              ; 32    ; Signed Integer                            ;
; x_uc_dma_size_w32           ; 11    ; Signed Integer                            ;
; x_uc_dma_nb_w32             ; 2048  ; Signed Integer                            ;
; x_chain_en                  ; '0'   ; Enumerated                                ;
; x_broadcast_en              ; '0'   ; Enumerated                                ;
; x_fifo_tx_size              ; 6     ; Signed Integer                            ;
; x_fifo_tx_thd_stop_flow     ; 32    ; Signed Integer                            ;
; x_fifo_tx_thd_restart_flow  ; 16    ; Signed Integer                            ;
; x_timeout_prescaler_ms_size ; 16    ; Signed Integer                            ;
; x_timeout_prescaler_ms_nb   ; 49998 ; Signed Integer                            ;
; x_timeout_ms_size           ; 10    ; Signed Integer                            ;
; x_timeout_ms                ; 500   ; Signed Integer                            ;
+-----------------------------+-------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB ;
+-------------------+-------+--------------------------------------------------------------------------+
; Parameter Name    ; Value ; Type                                                                     ;
+-------------------+-------+--------------------------------------------------------------------------+
; x_uc_data_size    ; 32    ; Signed Integer                                                           ;
; x_uc_dma_size_w32 ; 11    ; Signed Integer                                                           ;
; x_uc_dma_nb_w32   ; 2048  ; Signed Integer                                                           ;
; x_fifo_tx_size    ; 6     ; Signed Integer                                                           ;
; x_reset_active    ; '0'   ; Enumerated                                                               ;
+-------------------+-------+--------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component ;
+------------------------+--------------+----------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                                                                                 ;
+------------------------+--------------+----------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                                                           ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                                                         ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                                                         ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                                                       ;
; WIDTH                  ; 1            ; Signed Integer                                                                                                       ;
; POWER_UP_HIGH          ; OFF          ; Untyped                                                                                                              ;
; OE_REG                 ; UNREGISTERED ; Untyped                                                                                                              ;
; extend_oe_disable      ; OFF          ; Untyped                                                                                                              ;
; INTENDED_DEVICE_FAMILY ; Cyclone V    ; Untyped                                                                                                              ;
; DEVICE_FAMILY          ; Cyclone V    ; Untyped                                                                                                              ;
; CBXI_PARAMETER         ; ddio_out_b2j ; Untyped                                                                                                              ;
+------------------------+--------------+----------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                             ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                          ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                       ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                     ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                     ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                   ;
; LPM_WIDTH               ; 33          ; Signed Integer                                                                                   ;
; LPM_NUMWORDS            ; 64          ; Signed Integer                                                                                   ;
; LPM_WIDTHU              ; 6           ; Signed Integer                                                                                   ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                          ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                          ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                          ;
; USE_EAB                 ; ON          ; Untyped                                                                                          ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                          ;
; ENABLE_ECC              ; FALSE       ; Untyped                                                                                          ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                          ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                          ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                   ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                                                                   ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                          ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                          ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                                                          ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                          ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                          ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                          ;
; CBXI_PARAMETER          ; dcfifo_85n1 ; Untyped                                                                                          ;
+-------------------------+-------------+--------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                      ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                ;
+----------------+-------+-------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC ;
+-----------------+-------+--------------------------------------------------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                                                                   ;
+-----------------+-------+--------------------------------------------------------------------------------------------------------+
; x_reset_active  ; '0'   ; Enumerated                                                                                             ;
; x_din_byte_nb   ; 2     ; Signed Integer                                                                                         ;
; x_crc_din_width ; 4     ; Signed Integer                                                                                         ;
; x_crc_width     ; 16    ; Signed Integer                                                                                         ;
+-----------------+-------+--------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER ;
+-------------------------+-------+--------------------------------------------------------------------------+
; Parameter Name          ; Value ; Type                                                                     ;
+-------------------------+-------+--------------------------------------------------------------------------+
; x_reset_active          ; '0'   ; Enumerated                                                               ;
; x_nb_config_word16      ; 256   ; Signed Integer                                                           ;
; x_nb_config_word16_size ; 8     ; Signed Integer                                                           ;
; x_nb_dpram_size         ; 10    ; Signed Integer                                                           ;
; x_nb_devices_size       ; 2     ; Signed Integer                                                           ;
; x_fifo_tx_size          ; 6     ; Signed Integer                                                           ;
; x_fifo_tx_wr_duration   ; 00    ; Unsigned Binary                                                          ;
; x_enable_timeout        ; '1'   ; Enumerated                                                               ;
; x_timeout_ms_size       ; 10    ; Signed Integer                                                           ;
; x_timeout_ms            ; 500   ; Signed Integer                                                           ;
+-------------------------+-------+--------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER ;
+-----------------------------+-------+-----------------------------------------------------------------+
; Parameter Name              ; Value ; Type                                                            ;
+-----------------------------+-------+-----------------------------------------------------------------+
; x_reset_active              ; '0'   ; Enumerated                                                      ;
; x_nb_config_word16          ; 256   ; Signed Integer                                                  ;
; x_nb_dpram_size             ; 10    ; Signed Integer                                                  ;
; x_nb_devices_size           ; 2     ; Signed Integer                                                  ;
; x_chain_en                  ; '0'   ; Enumerated                                                      ;
; x_fifo_rx_rd_duration       ; 00    ; Unsigned Binary                                                 ;
; x_enable_timeout            ; '1'   ; Enumerated                                                      ;
; x_timeout_prescaler_ms_size ; 16    ; Signed Integer                                                  ;
; x_timeout_prescaler_ms_nb   ; 49998 ; Signed Integer                                                  ;
; x_timeout_ms_size           ; 10    ; Signed Integer                                                  ;
; x_timeout_ms                ; 500   ; Signed Integer                                                  ;
; x_broadcast_en              ; '0'   ; Enumerated                                                      ;
+-----------------------------+-------+-----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART ;
+------------------+-------------------+------------------------------------------------------------------+
; Parameter Name   ; Value             ; Type                                                             ;
+------------------+-------------------+------------------------------------------------------------------+
; x_reset_active   ; '0'               ; Enumerated                                                       ;
; x_no_prescaler   ; '0'               ; Enumerated                                                       ;
; x_prescaler_size ; 4                 ; Signed Integer                                                   ;
; x_fifo_width     ; 32                ; Signed Integer                                                   ;
; x_fifotx_depth   ; 6                 ; Signed Integer                                                   ;
; x_fiforx_depth   ; 6                 ; Signed Integer                                                   ;
; x_impl_type      ; WRAPPER_32RX_32TX ; String                                                           ;
+------------------+-------------------+------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1 ;
+------------------+-------+---------------------------------------------------------------------------------------------------------+
; Parameter Name   ; Value ; Type                                                                                                    ;
+------------------+-------+---------------------------------------------------------------------------------------------------------+
; x_reset_active   ; '0'   ; Enumerated                                                                                              ;
; x_no_prescaler   ; '0'   ; Enumerated                                                                                              ;
; x_prescaler_size ; 4     ; Signed Integer                                                                                          ;
; x_fifo_width     ; 32    ; Signed Integer                                                                                          ;
; x_fifotx_depth   ; 6     ; Signed Integer                                                                                          ;
+------------------+-------+---------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART ;
+------------------+-------+-------------------------------------------------------------------------------------------------------------------------+
; Parameter Name   ; Value ; Type                                                                                                                    ;
+------------------+-------+-------------------------------------------------------------------------------------------------------------------------+
; x_reset_active   ; '0'   ; Enumerated                                                                                                              ;
; x_no_prescaler   ; '0'   ; Enumerated                                                                                                              ;
; x_prescaler_size ; 4     ; Signed Integer                                                                                                          ;
+------------------+-------+-------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_bdgen:\g_dbgen:C_BDGEN ;
+------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name   ; Value ; Type                                                                                                                                                    ;
+------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active   ; '0'   ; Enumerated                                                                                                                                              ;
; x_prescaler_size ; 4     ; Signed Integer                                                                                                                                          ;
+------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                             ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; x_reset_active ; '0'   ; Enumerated                                                                                                                                       ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component ;
+-------------------------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                            ; Value       ; Type                                                                                                                                                    ;
+-------------------------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; ACF_DISABLE_EMBEDDED_TIMING_CONSTRAINT    ; FALSE       ; Untyped                                                                                                                                                 ;
; ACF_DISABLE_MLAB_RAM_USE                  ; FALSE       ; Untyped                                                                                                                                                 ;
; ADD_RAM_OUTPUT_REGISTER                   ; OFF         ; Untyped                                                                                                                                                 ;
; ADD_USEDW_MSB_BIT                         ; OFF         ; Untyped                                                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED                   ; FALSE       ; Untyped                                                                                                                                                 ;
; DELAY_RDUSEDW                             ; 1           ; Untyped                                                                                                                                                 ;
; DELAY_WRUSEDW                             ; 1           ; Untyped                                                                                                                                                 ;
; DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT ; FALSE       ; Untyped                                                                                                                                                 ;
; ENABLE_ECC                                ; FALSE       ; Untyped                                                                                                                                                 ;
; LPM_NUMWORDS                              ; 64          ; Signed Integer                                                                                                                                          ;
; LPM_SHOWAHEAD                             ; OFF         ; Untyped                                                                                                                                                 ;
; LPM_WIDTH                                 ; 32          ; Signed Integer                                                                                                                                          ;
; LPM_WIDTH_R                               ; 8           ; Signed Integer                                                                                                                                          ;
; LPM_WIDTHU                                ; 6           ; Signed Integer                                                                                                                                          ;
; LPM_WIDTHU_R                              ; 8           ; Signed Integer                                                                                                                                          ;
; MAXIMIZE_SPEED                            ; 5           ; Untyped                                                                                                                                                 ;
; OVERFLOW_CHECKING                         ; ON          ; Untyped                                                                                                                                                 ;
; RAM_BLOCK_TYPE                            ; AUTO        ; Untyped                                                                                                                                                 ;
; RDSYNC_DELAYPIPE                          ; 4           ; Signed Integer                                                                                                                                          ;
; READ_ACLR_SYNCH                           ; OFF         ; Untyped                                                                                                                                                 ;
; UNDERFLOW_CHECKING                        ; ON          ; Untyped                                                                                                                                                 ;
; USE_EAB                                   ; ON          ; Untyped                                                                                                                                                 ;
; WRITE_ACLR_SYNCH                          ; OFF         ; Untyped                                                                                                                                                 ;
; WRSYNC_DELAYPIPE                          ; 4           ; Signed Integer                                                                                                                                          ;
; CBXI_PARAMETER                            ; dcfifo_8tq1 ; Untyped                                                                                                                                                 ;
+-------------------------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component ;
+-------------------------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                            ; Value       ; Type                                                                                                                                                    ;
+-------------------------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; ACF_DISABLE_EMBEDDED_TIMING_CONSTRAINT    ; FALSE       ; Untyped                                                                                                                                                 ;
; ACF_DISABLE_MLAB_RAM_USE                  ; FALSE       ; Untyped                                                                                                                                                 ;
; ADD_RAM_OUTPUT_REGISTER                   ; OFF         ; Untyped                                                                                                                                                 ;
; ADD_USEDW_MSB_BIT                         ; OFF         ; Untyped                                                                                                                                                 ;
; CLOCKS_ARE_SYNCHRONIZED                   ; FALSE       ; Untyped                                                                                                                                                 ;
; DELAY_RDUSEDW                             ; 1           ; Untyped                                                                                                                                                 ;
; DELAY_WRUSEDW                             ; 1           ; Untyped                                                                                                                                                 ;
; DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT ; FALSE       ; Untyped                                                                                                                                                 ;
; ENABLE_ECC                                ; FALSE       ; Untyped                                                                                                                                                 ;
; LPM_NUMWORDS                              ; 256         ; Signed Integer                                                                                                                                          ;
; LPM_SHOWAHEAD                             ; OFF         ; Untyped                                                                                                                                                 ;
; LPM_WIDTH                                 ; 8           ; Signed Integer                                                                                                                                          ;
; LPM_WIDTH_R                               ; 32          ; Signed Integer                                                                                                                                          ;
; LPM_WIDTHU                                ; 8           ; Signed Integer                                                                                                                                          ;
; LPM_WIDTHU_R                              ; 6           ; Signed Integer                                                                                                                                          ;
; MAXIMIZE_SPEED                            ; 5           ; Untyped                                                                                                                                                 ;
; OVERFLOW_CHECKING                         ; ON          ; Untyped                                                                                                                                                 ;
; RAM_BLOCK_TYPE                            ; AUTO        ; Untyped                                                                                                                                                 ;
; RDSYNC_DELAYPIPE                          ; 4           ; Signed Integer                                                                                                                                          ;
; READ_ACLR_SYNCH                           ; OFF         ; Untyped                                                                                                                                                 ;
; UNDERFLOW_CHECKING                        ; ON          ; Untyped                                                                                                                                                 ;
; USE_EAB                                   ; ON          ; Untyped                                                                                                                                                 ;
; WRITE_ACLR_SYNCH                          ; OFF         ; Untyped                                                                                                                                                 ;
; WRSYNC_DELAYPIPE                          ; 4           ; Signed Integer                                                                                                                                          ;
; CBXI_PARAMETER                            ; dcfifo_a5q1 ; Untyped                                                                                                                                                 ;
+-------------------------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component ;
+-------------------------+-------------+---------------------------------------------------+
; Parameter Name          ; Value       ; Type                                              ;
+-------------------------+-------------+---------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                           ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                        ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                      ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                      ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                    ;
; LPM_WIDTH               ; 33          ; Signed Integer                                    ;
; LPM_NUMWORDS            ; 1024        ; Signed Integer                                    ;
; LPM_WIDTHU              ; 10          ; Signed Integer                                    ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                           ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                           ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                           ;
; USE_EAB                 ; ON          ; Untyped                                           ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                           ;
; ENABLE_ECC              ; FALSE       ; Untyped                                           ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                           ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                           ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                    ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                    ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                           ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                           ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                           ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                           ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                           ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                           ;
; CBXI_PARAMETER          ; dcfifo_6tr1 ; Untyped                                           ;
+-------------------------+-------------+---------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UGB_CFG_DPRAM:C_DPRAM|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+----------------------------------------+
; Parameter Name                     ; Value                ; Type                                   ;
+------------------------------------+----------------------+----------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                             ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                           ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                           ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                         ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                ;
; WIDTH_A                            ; 16                   ; Signed Integer                         ;
; WIDTHAD_A                          ; 10                   ; Signed Integer                         ;
; NUMWORDS_A                         ; 1024                 ; Signed Integer                         ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                ;
; WIDTH_B                            ; 16                   ; Signed Integer                         ;
; WIDTHAD_B                          ; 10                   ; Signed Integer                         ;
; NUMWORDS_B                         ; 1024                 ; Signed Integer                         ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                ;
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer                         ;
; WIDTH_BYTEENA_B                    ; 1                    ; Signed Integer                         ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                ;
; BYTE_SIZE                          ; 8                    ; Signed Integer                         ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                ;
; INIT_FILE                          ; UNUSED               ; Untyped                                ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                ;
; MAXIMUM_DEPTH                      ; 0                    ; Signed Integer                         ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                                ;
; CLOCK_ENABLE_INPUT_B               ; BYPASS               ; Untyped                                ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                ;
; CLOCK_ENABLE_OUTPUT_B              ; BYPASS               ; Untyped                                ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                ;
; WIDTH_ECCSTATUS                    ; 3                    ; Signed Integer                         ;
; DEVICE_FAMILY                      ; Cyclone V            ; Untyped                                ;
; CBXI_PARAMETER                     ; altsyncram_s1v3      ; Untyped                                ;
+------------------------------------+----------------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: USER_GET_CONFIG_RANGE_RD:C_HOUSEKEEPING_USER_GET ;
+------------------------+-------+--------------------------------------------------------------+
; Parameter Name         ; Value ; Type                                                         ;
+------------------------+-------+--------------------------------------------------------------+
; x_reset_active         ; '0'   ; Enumerated                                                   ;
; x_user_get_cmd_size    ; 8     ; Signed Integer                                               ;
; x_sel_user_get_cmd_lsb ; 0     ; Signed Integer                                               ;
; x_sel_user_get_cmd_msb ; 8     ; Signed Integer                                               ;
+------------------------+-------+--------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: USER_GET_CONFIG_RANGE_RD:C_PEDESTALS_USER_GET ;
+------------------------+-------+-----------------------------------------------------------+
; Parameter Name         ; Value ; Type                                                      ;
+------------------------+-------+-----------------------------------------------------------+
; x_reset_active         ; '0'   ; Enumerated                                                ;
; x_user_get_cmd_size    ; 8     ; Signed Integer                                            ;
; x_sel_user_get_cmd_lsb ; 9     ; Signed Integer                                            ;
; x_sel_user_get_cmd_msb ; 136   ; Signed Integer                                            ;
+------------------------+-------+-----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: UFP_USER_SETGET_ACK:C_GET_ACK ;
+----------------+-------+---------------------------------------------------+
; Parameter Name ; Value ; Type                                              ;
+----------------+-------+---------------------------------------------------+
; x_user_nb      ; 2     ; Signed Integer                                    ;
+----------------+-------+---------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component ;
+-------------------------+-------------+-----------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                ;
+-------------------------+-------------+-----------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                             ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                          ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                        ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                        ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                      ;
; LPM_WIDTH               ; 9           ; Signed Integer                                      ;
; LPM_NUMWORDS            ; 1024        ; Signed Integer                                      ;
; LPM_WIDTHU              ; 10          ; Signed Integer                                      ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                             ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                             ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                             ;
; USE_EAB                 ; ON          ; Untyped                                             ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                             ;
; ENABLE_ECC              ; FALSE       ; Untyped                                             ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                             ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                             ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                      ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                      ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                             ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                             ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                             ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                             ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                             ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                             ;
; CBXI_PARAMETER          ; dcfifo_t7q1 ; Untyped                                             ;
+-------------------------+-------------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component ;
+-------------------------+-------------+-----------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                ;
+-------------------------+-------------+-----------------------------------------------------+
; WIDTH_BYTEENA           ; 1           ; Untyped                                             ;
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                          ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                        ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                        ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                      ;
; LPM_WIDTH               ; 8           ; Signed Integer                                      ;
; LPM_NUMWORDS            ; 16          ; Signed Integer                                      ;
; LPM_WIDTHU              ; 4           ; Signed Integer                                      ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                             ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                             ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                             ;
; USE_EAB                 ; ON          ; Untyped                                             ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                             ;
; ENABLE_ECC              ; FALSE       ; Untyped                                             ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                             ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                             ;
; RDSYNC_DELAYPIPE        ; 4           ; Signed Integer                                      ;
; WRSYNC_DELAYPIPE        ; 4           ; Signed Integer                                      ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                             ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                             ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                             ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                             ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                             ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                                             ;
; CBXI_PARAMETER          ; dcfifo_12q1 ; Untyped                                             ;
+-------------------------+-------------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: L0_FIFO:C_L0_FIFO|scfifo:scfifo_component ;
+-------------------------+-------------+------------------------------------------------+
; Parameter Name          ; Value       ; Type                                           ;
+-------------------------+-------------+------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                     ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                   ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                   ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                 ;
; lpm_width               ; 32          ; Signed Integer                                 ;
; LPM_NUMWORDS            ; 64          ; Signed Integer                                 ;
; LPM_WIDTHU              ; 6           ; Signed Integer                                 ;
; LPM_SHOWAHEAD           ; ON          ; Untyped                                        ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                        ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                        ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                        ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                        ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                        ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                        ;
; ENABLE_ECC              ; FALSE       ; Untyped                                        ;
; USE_EAB                 ; ON          ; Untyped                                        ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                        ;
; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                        ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                        ;
; CBXI_PARAMETER          ; scfifo_3e91 ; Untyped                                        ;
+-------------------------+-------------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------+
; dcfifo Parameter Settings by Entity Instance                                                                             ;
+----------------------------+---------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                       ;
+----------------------------+---------------------------------------------------------------------------------------------+
; Number of entity instances ; 4                                                                                           ;
; Entity Instance            ; UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                                                                  ;
;     -- LPM_WIDTH           ; 33                                                                                          ;
;     -- LPM_NUMWORDS        ; 64                                                                                          ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                         ;
;     -- USE_EAB             ; ON                                                                                          ;
; Entity Instance            ; UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component                                                ;
;     -- FIFO Type           ; Dual Clock                                                                                  ;
;     -- LPM_WIDTH           ; 33                                                                                          ;
;     -- LPM_NUMWORDS        ; 1024                                                                                        ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                         ;
;     -- USE_EAB             ; ON                                                                                          ;
; Entity Instance            ; SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component                                              ;
;     -- FIFO Type           ; Dual Clock                                                                                  ;
;     -- LPM_WIDTH           ; 9                                                                                           ;
;     -- LPM_NUMWORDS        ; 1024                                                                                        ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                         ;
;     -- USE_EAB             ; ON                                                                                          ;
; Entity Instance            ; SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component                                              ;
;     -- FIFO Type           ; Dual Clock                                                                                  ;
;     -- LPM_WIDTH           ; 8                                                                                           ;
;     -- LPM_NUMWORDS        ; 16                                                                                          ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                         ;
;     -- USE_EAB             ; ON                                                                                          ;
+----------------------------+---------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance                           ;
+----------------------------+-------------------------------------------+
; Name                       ; Value                                     ;
+----------------------------+-------------------------------------------+
; Number of entity instances ; 1                                         ;
; Entity Instance            ; L0_FIFO:C_L0_FIFO|scfifo:scfifo_component ;
;     -- FIFO Type           ; Single Clock                              ;
;     -- lpm_width           ; 32                                        ;
;     -- LPM_NUMWORDS        ; 64                                        ;
;     -- LPM_SHOWAHEAD       ; ON                                        ;
;     -- USE_EAB             ; ON                                        ;
+----------------------------+-------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                                                  ;
+-------------------------------------------+-------------------------------------------------------+
; Name                                      ; Value                                                 ;
+-------------------------------------------+-------------------------------------------------------+
; Number of entity instances                ; 1                                                     ;
; Entity Instance                           ; UGB_CFG_DPRAM:C_DPRAM|altsyncram:altsyncram_component ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                             ;
;     -- WIDTH_A                            ; 16                                                    ;
;     -- NUMWORDS_A                         ; 1024                                                  ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                          ;
;     -- WIDTH_B                            ; 16                                                    ;
;     -- NUMWORDS_B                         ; 1024                                                  ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                          ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                             ;
+-------------------------------------------+-------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "fee_controller:C_FEECONTROLLER"                                                                     ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                 ; Type   ; Severity ; Details                                                                             ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_acq_cmd_reg[15..3] ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_acq_ack            ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_debug              ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "serdes:SERDES|GCLK:RxClk_Buf|GCLK_altclkctrl_0:altclkctrl_0|GCLK_altclkctrl_0_sub:GCLK_altclkctrl_0_sub_component" ;
+-------------+-------+----------+--------------------------------------------------------------------------------------------------------------+
; Port        ; Type  ; Severity ; Details                                                                                                      ;
+-------------+-------+----------+--------------------------------------------------------------------------------------------------------------+
; ena         ; Input ; Info     ; Stuck at VCC                                                                                                 ;
; inclk[3..1] ; Input ; Info     ; Stuck at GND                                                                                                 ;
+-------------+-------+----------+--------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------+
; Port Connectivity Checks: "USER_GET_CONFIG_RANGE_RD:C_HOUSEKEEPING_USER_GET" ;
+-----------------------+-------+----------+-----------------------------------+
; Port                  ; Type  ; Severity ; Details                           ;
+-----------------------+-------+----------+-----------------------------------+
; x_registers[143..136] ; Input ; Info     ; Stuck at GND                      ;
+-----------------------+-------+----------+-----------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UGB_DATA_FIFO:C_FIFO"                                                                  ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                             ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; wrusedw ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; rdusedw ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER" ;
+------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+
; Port             ; Type   ; Severity ; Details                                                                                                           ;
+------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+
; x_rd             ; Input  ; Info     ; Stuck at VCC                                                                                                      ;
; x_overrun_err    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_state_g        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_shift_g        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_count_g        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_clk_count_g    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_start_detect_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_parity_calc_g  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_parity_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
; x_clkpulse_g     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                               ;
+------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER" ;
+-------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+
; Port        ; Type   ; Severity ; Details                                                                                                            ;
+-------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+
; x_ready     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                ;
; x_state_g   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                ;
; x_parity_g  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                ;
; x_shift_g   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                ;
; x_tx_done_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                ;
+-------------+--------+----------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_bdgen:\g_dbgen:C_BDGEN" ;
+---------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+
; Port          ; Type   ; Severity ; Details                                                                                                                       ;
+---------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+
; x_counter16_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                           ;
; x_counter_g   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                           ;
+---------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART"                                      ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                             ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_baudrate16      ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_parity_en       ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_parity_odd      ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_fiforx_rd_usedw ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_error           ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_error_clr       ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_flush           ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_pulse_out_g     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_pulse16_out_g   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER"                                         ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                    ; Type   ; Severity ; Details                                                                             ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_lib_fw_version[1..0]  ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_lib_fw_version[15..4] ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_lib_fw_version[3]     ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_lib_fw_version[2]     ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_fifo_tx_wr_lsb        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC" ;
+-----------------------+-------+----------+----------------------------------------------------------------------+
; Port                  ; Type  ; Severity ; Details                                                              ;
+-----------------------+-------+----------+----------------------------------------------------------------------+
; x_crc_init            ; Input ; Info     ; Stuck at VCC                                                         ;
; x_crc_final           ; Input ; Info     ; Stuck at GND                                                         ;
; x_crc_din_msb_1st     ; Input ; Info     ; Stuck at GND                                                         ;
; x_crc_reflect_crc_din ; Input ; Info     ; Stuck at VCC                                                         ;
; x_crc_reflect_crc     ; Input ; Info     ; Stuck at GND                                                         ;
+-----------------------+-------+----------+----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK" ;
+----------+-------+----------+-----------------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                                     ;
+----------+-------+----------+-----------------------------------------------------------------------------+
; datain_h ; Input ; Info     ; Stuck at GND                                                                ;
; datain_l ; Input ; Info     ; Stuck at VCC                                                                ;
+----------+-------+----------+-----------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB"                                  ;
+------------+--------+----------+-------------------------------------------------------------------------------------+
; Port       ; Type   ; Severity ; Details                                                                             ;
+------------+--------+----------+-------------------------------------------------------------------------------------+
; x_zlp_rq_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFP_WRAPPER_USB_UART:C_WRAPPER_USB"                                                                    ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                    ; Type   ; Severity ; Details                                                                             ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+
; x_uart_tx_en            ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_uart_rtsn             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_uart_ctsn             ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_usb_stop_flow         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_sc_config             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_board_id_ans_dis      ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_board_id[6..4]        ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_board_id[3]           ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_board_id[2]           ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_board_id[1]           ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_board_id[0]           ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_fw_version[15..5]     ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_fw_version[1..0]      ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_fw_version[4]         ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_fw_version[3]         ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_fw_version[2]         ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_hw_version            ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_product_id[15..3]     ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_product_id[2]         ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_product_id[1]         ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_product_id[0]         ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_device_valid_word     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_param_out[15..6]      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_user_set_req          ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_user_set_ack          ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_user_set_error        ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_user_set_error_d      ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_user_set_cmd_req      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_user_set_cmd          ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_user_set_cmd_ack      ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_user_set_cmd_error    ; Input  ; Info     ; Stuck at VCC                                                                        ;
; x_user_set_cmd_error_d  ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_user_get_cmd[15..8]   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_user_get_error        ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_user_get_error_d      ; Input  ; Info     ; Stuck at GND                                                                        ;
; x_state_g               ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_wr_cnt_g              ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_data_av_g             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fiforx_wr_req_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fiforx_wr_full_g      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fiforx_rd_req_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fiforx_rd_dout_g      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fiforx_rd_empty_g     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fifotx_rd_req_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fifotx_rd_empty_g     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fifotx_wr_req_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fifotx_wr_full_g      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fifotx_wr_din_g       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fiforeadout_tx_wr_g   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_fiforeadout_tx_full_g ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_crc_dout_av_g         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_crc_dout_g            ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; x_answer_rq_g           ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; arriav_clkena         ; 1                           ;
; arriav_ddio_out       ; 1                           ;
; arriav_ff             ; 5317                        ;
;     CLR               ; 576                         ;
;     CLR SCLR          ; 50                          ;
;     CLR SLD           ; 11                          ;
;     ENA               ; 68                          ;
;     ENA CLR           ; 4366                        ;
;     ENA CLR SCLR      ; 61                          ;
;     ENA CLR SCLR SLD  ; 16                          ;
;     ENA CLR SLD       ; 32                          ;
;     plain             ; 137                         ;
; arriav_io_obuf        ; 50                          ;
; arriav_lcell_comb     ; 1935                        ;
;     arith             ; 171                         ;
;         0 data inputs ; 2                           ;
;         1 data inputs ; 160                         ;
;         2 data inputs ; 9                           ;
;     extend            ; 10                          ;
;         7 data inputs ; 10                          ;
;     normal            ; 1742                        ;
;         0 data inputs ; 2                           ;
;         1 data inputs ; 42                          ;
;         2 data inputs ; 152                         ;
;         3 data inputs ; 158                         ;
;         4 data inputs ; 235                         ;
;         5 data inputs ; 203                         ;
;         6 data inputs ; 950                         ;
;     shared            ; 12                          ;
;         2 data inputs ; 12                          ;
; boundary_port         ; 207                         ;
; generic_pll           ; 4                           ;
; stratixv_ram_block    ; 147                         ;
;                       ;                             ;
; Max LUT depth         ; 5.00                        ;
; Average LUT depth     ; 2.23                        ;
+-----------------------+-----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:03     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition
    Info: Processing started: Wed Jun 18 10:51:16 2025
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FEE_Control -c FEE_Control
Info (20032): Parallel compilation is enabled and will use up to 4 processors
Info (12248): Elaborating Platform Designer system entity "GCLK.qsys"
Info (12250): 2025.06.18.10:51:24 Progress: Loading FEE_Control/GCLK.qsys
Info (12250): 2025.06.18.10:51:24 Progress: Reading input file
Info (12250): 2025.06.18.10:51:24 Progress: Adding altclkctrl_0 [altclkctrl 18.0]
Info (12250): 2025.06.18.10:51:25 Progress: Parameterizing module altclkctrl_0
Info (12250): 2025.06.18.10:51:25 Progress: Building connections
Info (12250): 2025.06.18.10:51:25 Progress: Parameterizing connections
Info (12250): 2025.06.18.10:51:25 Progress: Validating
Info (12250): 2025.06.18.10:51:25 Progress: Done reading input file
Info (12250): 2025.06.18.10:51:25 : GCLK.altclkctrl_0: Targeting device family: Cyclone V.
Info (12250): 2025.06.18.10:51:25 : GCLK.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs.
Info (12250): 2025.06.18.10:51:25 : GCLK.altclkctrl_0: The register mode of port 'ena' is unavailable while 'ena' port not added. 
Info (12250): GCLK: Generating GCLK "GCLK" for QUARTUS_SYNTH
Info (12250): Altclkctrl_0: Generating top-level entity GCLK_altclkctrl_0.
Info (12250): Altclkctrl_0: "GCLK" instantiated altclkctrl "altclkctrl_0"
Info (12250): GCLK: Done "GCLK" with 2 modules, 2 files
Info (12249): Finished elaborating Platform Designer system entity "GCLK.qsys"
Info (12021): Found 2 design units, including 1 entities, in source file src/serial_communication/decoder_4b5b.vhd
    Info (12022): Found design unit 1: decoder_4b5b-syn File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/decoder_4b5b.vhd Line: 28
    Info (12023): Found entity 1: decoder_4b5b File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/decoder_4b5b.vhd Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file src/serial_communication/4b5b_encoder.vhd
    Info (12022): Found design unit 1: encoder_4b5b-syn File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/4b5b_encoder.vhd Line: 29
    Info (12023): Found entity 1: encoder_4b5b File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/4b5b_encoder.vhd Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file src/serial_communication/serializer.vhd
    Info (12022): Found design unit 1: serializer-syn File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/Serializer.vhd Line: 39
    Info (12023): Found entity 1: serializer File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/Serializer.vhd Line: 23
Info (12021): Found 2 design units, including 1 entities, in source file src/serial_communication/serdes.vhd
    Info (12022): Found design unit 1: serdes-A_serdes File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/Serdes.vhd Line: 70
    Info (12023): Found entity 1: serdes File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/Serdes.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file src/serial_communication/deserializer.vhd
    Info (12022): Found design unit 1: deserializer-syn File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/Deserializer.vhd Line: 43
    Info (12023): Found entity 1: deserializer File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/Deserializer.vhd Line: 21
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/c_cyclone5/src/ser_uart_fifo_tx32.vhd
    Info (12022): Found design unit 1: ser_uart_fifo_tx32-SYN File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd Line: 59
    Info (12023): Found entity 1: SER_UART_FIFO_TX32 File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/c_cyclone5/src/ser_uart_fifo_rx32.vhd
    Info (12022): Found design unit 1: ser_uart_fifo_rx32-SYN File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd Line: 58
    Info (12023): Found entity 1: SER_UART_FIFO_RX32 File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file src/fee_controller/fee_controller.vhd
    Info (12022): Found design unit 1: fee_controller-syn File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/fee_controller/fee_controller.vhd Line: 65
    Info (12023): Found entity 1: fee_controller File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/fee_controller/fee_controller.vhd Line: 18
Info (12021): Found 2 design units, including 1 entities, in source file src/fee_control.vhd
    Info (12022): Found design unit 1: FEE_Control-Behavioral File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 201
    Info (12023): Found entity 1: FEE_Control File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 12
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/u_util/exp/u_size.vhd
    Info (12022): Found design unit 1: U_Size File: J:/vhdl_db/trunk/lib/u_util/exp/u_size.vhd Line: 10
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/u_util/exp/u_util.vhd
    Info (12022): Found design unit 1: u_util File: J:/vhdl_db/trunk/lib/u_util/exp/u_util.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/u_util/src/u_onepulse.vhd
    Info (12022): Found design unit 1: U_OnePulse-A_behavioral File: J:/vhdl_db/trunk/lib/u_util/src/u_onepulse.vhd Line: 26
    Info (12023): Found entity 1: U_OnePulse File: J:/vhdl_db/trunk/lib/u_util/src/u_onepulse.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/usb_l2_tx_fifo.vhd
    Info (12022): Found design unit 1: usb_l2_tx_fifo-SYN File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd Line: 59
    Info (12023): Found entity 1: USB_L2_TX_FIFO File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd Line: 42
Info (12021): Found 2 design units, including 0 entities, in source file /vhdl_db/trunk/lib/usb_usb/exp/usb_usb.vhd
    Info (12022): Found design unit 1: usb_usb File: J:/vhdl_db/trunk/lib/usb_usb/exp/USB_USB.vhd Line: 11
    Info (12022): Found design unit 2: usb_usb-body File: J:/vhdl_db/trunk/lib/usb_usb/exp/USB_USB.vhd Line: 245
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/usb_uc_pclk.vhd
    Info (12022): Found design unit 1: usb_uc_pclk-SYN File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 53
    Info (12023): Found entity 1: USB_UC_PCLK File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/usb_usb/src/usb_usb_reader.vhd
    Info (12022): Found design unit 1: USB_USB_Reader-Behavioral File: J:/vhdl_db/trunk/lib/usb_usb/src/USB_USB_Reader.vhd Line: 49
    Info (12023): Found entity 1: USB_USB_Reader File: J:/vhdl_db/trunk/lib/usb_usb/src/USB_USB_Reader.vhd Line: 11
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/exp/ser_serialcommunication.vhd
    Info (12022): Found design unit 1: ser_serialCommunication File: J:/vhdl_db/trunk/lib/ser_serialCommunication/exp/ser_serialCommunication.vhd Line: 14
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/exp/ser_crc_pck.vhd
    Info (12022): Found design unit 1: ser_crc_pck File: J:/vhdl_db/trunk/lib/ser_serialCommunication/exp/ser_crc_pck.vhd Line: 9
Info (12021): Found 2 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_crc_pck_polynomial.vhd
    Info (12022): Found design unit 1: ser_crc_pck_polynomial File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc_pck_polynomial.vhd Line: 13
    Info (12022): Found design unit 2: ser_crc_pck_polynomial-body File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc_pck_polynomial.vhd Line: 78
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_crc.vhd
    Info (12022): Found design unit 1: ser_crc-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc.vhd Line: 44
    Info (12023): Found entity 1: ser_crc File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc.vhd Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/crc_pol/ser_crc_pol16_din16_d4_1a2eb.vhd
    Info (12022): Found design unit 1: ser_crc_pol16_DIN16_D4_1a2eb-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd Line: 32
    Info (12023): Found entity 1: ser_crc_pol16_DIN16_D4_1a2eb File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_uart_ser.vhd
    Info (12022): Found design unit 1: ser_uart_ser-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_ser.vhd Line: 45
    Info (12023): Found entity 1: ser_uart_ser File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_ser.vhd Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_uart_deser.vhd
    Info (12022): Found design unit 1: ser_uart_deser-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_deser.vhd Line: 50
    Info (12023): Found entity 1: ser_uart_deser File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_deser.vhd Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_data_5_bits_filter.vhd
    Info (12022): Found design unit 1: ser_data_5_bits_filter-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_data_5_bits_filter.vhd Line: 21
    Info (12023): Found entity 1: ser_data_5_bits_filter File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_data_5_bits_filter.vhd Line: 11
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_uart_bdgen.vhd
    Info (12022): Found design unit 1: ser_uart_bdgen-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_bdgen.vhd Line: 38
    Info (12023): Found entity 1: ser_uart_bdgen File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_bdgen.vhd Line: 10
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_uart.vhd
    Info (12022): Found design unit 1: ser_uart-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart.vhd Line: 65
    Info (12023): Found entity 1: ser_uart File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart.vhd Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_uart_wrapper.vhd
    Info (12022): Found design unit 1: ser_uart_wrapper-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper.vhd Line: 76
    Info (12023): Found entity 1: ser_uart_wrapper File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper.vhd Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ser_serialcommunication/src/ser_uart_wrapper32.vhd
    Info (12022): Found design unit 1: ser_uart_wrapper32-A_Behavioral File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper32.vhd Line: 73
    Info (12023): Found entity 1: ser_uart_wrapper32 File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper32.vhd Line: 12
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/exp/ufp_usbfrontendprotocol.vhd
    Info (12022): Found design unit 1: UFP_UsbFrontEndProtocol File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_UsbFrontEndProtocol.vhd Line: 16
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/exp/ufp_fw_version.vhd
    Info (12022): Found design unit 1: UFP_fw_version File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_fw_version.vhd Line: 11
Info (12021): Found 1 design units, including 0 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/exp/ufp_protocol.vhd
    Info (12022): Found design unit 1: UFP_Protocol File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/exp/UFP_Protocol.vhd Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_decoder.vhd
    Info (12022): Found design unit 1: UFP_DECODER-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Decoder.vhd Line: 76
    Info (12023): Found entity 1: UFP_DECODER File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Decoder.vhd Line: 9
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_encoder_uart.vhd
    Info (12022): Found design unit 1: UFP_ENCODER_UART-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Encoder_uart.vhd Line: 68
    Info (12023): Found entity 1: UFP_ENCODER_UART File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_Encoder_uart.vhd Line: 10
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_wrapper_usb_uart.vhd
    Info (12022): Found design unit 1: UFP_WRAPPER_USB_UART-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 135
    Info (12023): Found entity 1: UFP_WRAPPER_USB_UART File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_user_get_config.vhd
    Info (12022): Found design unit 1: UFP_USER_GET_CONFIG-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_GET_CONFIG.vhd Line: 39
    Info (12023): Found entity 1: UFP_USER_GET_CONFIG File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_GET_CONFIG.vhd Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_user_set_config.vhd
    Info (12022): Found design unit 1: UFP_USER_SET_CONFIG-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SET_CONFIG.vhd Line: 43
    Info (12023): Found entity 1: UFP_USER_SET_CONFIG File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SET_CONFIG.vhd Line: 17
Info (12021): Found 2 design units, including 1 entities, in source file /vhdl_db/trunk/lib/ufp_usbfrontendprotocol/src/ufp_user_setget_ack.vhd
    Info (12022): Found design unit 1: UFP_USER_SETGET_ACK-Behavioral File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SETGET_ACK.vhd Line: 22
    Info (12023): Found entity 1: UFP_USER_SETGET_ACK File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_USER_SETGET_ACK.vhd Line: 10
Info (12021): Found 2 design units, including 1 entities, in source file src/ugb_data_fifo.vhd
    Info (12022): Found design unit 1: ugb_data_fifo-SYN File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/UGB_DATA_FIFO.vhd Line: 60
    Info (12023): Found entity 1: UGB_DATA_FIFO File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/UGB_DATA_FIFO.vhd Line: 42
Info (12021): Found 1 design units, including 0 entities, in source file src/ugb_global_const.vhd
    Info (12022): Found design unit 1: UGB_GLOBAL_CONST File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/UGB_GLOBAL_CONST.vhd Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file src/serdes_tx_fifo.vhd
    Info (12022): Found design unit 1: serdes_tx_fifo-SYN File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/SERDES_TX_FIFO.vhd Line: 58
    Info (12023): Found entity 1: SERDES_TX_FIFO File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/SERDES_TX_FIFO.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file src/serdes_rx_fifo.vhd
    Info (12022): Found design unit 1: serdes_rx_fifo-SYN File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/SERDES_RX_FIFO.vhd Line: 58
    Info (12023): Found entity 1: SERDES_RX_FIFO File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/SERDES_RX_FIFO.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file src/ugb_cfg_dpram.vhd
    Info (12022): Found design unit 1: ugb_cfg_dpram-SYN File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/UGB_CFG_DPRAM.vhd Line: 55
    Info (12023): Found entity 1: UGB_CFG_DPRAM File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/UGB_CFG_DPRAM.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file src/l0_fifo.vhd
    Info (12022): Found design unit 1: l0_fifo-SYN File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/L0_FIFO.vhd Line: 57
    Info (12023): Found entity 1: L0_FIFO File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/L0_FIFO.vhd Line: 42
Info (12021): Found 2 design units, including 1 entities, in source file src/pll_gpio/pll_60.vhd
    Info (12022): Found design unit 1: PLL_60-rtl File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/PLL_GPIO/PLL_60.vhd Line: 23
    Info (12023): Found entity 1: PLL_60 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/PLL_GPIO/PLL_60.vhd Line: 11
Info (12021): Found 1 design units, including 1 entities, in source file src/pll_gpio/pll_60/pll_60_0002.v
    Info (12023): Found entity 1: PLL_60_0002 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/PLL_GPIO/PLL_60/PLL_60_0002.v Line: 2
Info (12021): Found 2 design units, including 1 entities, in source file src/user_get_config_range_rd.vhd
    Info (12022): Found design unit 1: USER_GET_CONFIG_RANGE_RD-Behavioral File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/USER_GET_CONFIG_RANGE_RD.vhd Line: 41
    Info (12023): Found entity 1: USER_GET_CONFIG_RANGE_RD File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/USER_GET_CONFIG_RANGE_RD.vhd Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/gclk/gclk.v
    Info (12023): Found entity 1: GCLK File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/ip/gclk/gclk.v Line: 6
Info (12021): Found 2 design units, including 2 entities, in source file db/ip/gclk/submodules/gclk_altclkctrl_0.v
    Info (12023): Found entity 1: GCLK_altclkctrl_0_sub File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/ip/gclk/submodules/gclk_altclkctrl_0.v Line: 28
    Info (12023): Found entity 2: GCLK_altclkctrl_0 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/ip/gclk/submodules/gclk_altclkctrl_0.v Line: 79
Info (12127): Elaborating entity "FEE_Control" for the top level hierarchy
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(57): used implicit default value for signal "x_3B_TX33" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 57
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(62): used implicit default value for signal "x_3B_TX25" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 62
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(64): used implicit default value for signal "x_3B_TX29" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 64
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(65): used implicit default value for signal "x_3B_TX32" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 65
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(66): used implicit default value for signal "x_3B_TX40" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 66
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(70): used implicit default value for signal "x_4A_TX57" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 70
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(71): used implicit default value for signal "x_4A_TX60" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 71
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(73): used implicit default value for signal "x_4A_TX64" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 73
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(76): used implicit default value for signal "x_4A_TXP49" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 76
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(77): used implicit default value for signal "x_4A_TXN49" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 77
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(78): used implicit default value for signal "x_4A_TXP53" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 78
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(81): used implicit default value for signal "x_4A_TXP41" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 81
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(82): used implicit default value for signal "x_4A_TXN41" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 82
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(83): used implicit default value for signal "x_4A_TXP45" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 83
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(87): used implicit default value for signal "x_4A_TXN56" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 87
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(89): used implicit default value for signal "x_4A_RXP59" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 89
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(90): used implicit default value for signal "x_4A_RXN59" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 90
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(91): used implicit default value for signal "x_4A_TXP61" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 91
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(92): used implicit default value for signal "x_4A_TXN61" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 92
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(95): used implicit default value for signal "x_4A_TXN52" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 95
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(97): used implicit default value for signal "x_3B_TXP28" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 97
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(98): used implicit default value for signal "x_3B_TXN28" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 98
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(99): used implicit default value for signal "x_4A_TXP44" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 99
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(100): used implicit default value for signal "x_4A_TXN44" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 100
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(121): used implicit default value for signal "x_5A_TXP1" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 121
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(122): used implicit default value for signal "x_5A_TXN1" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 122
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(125): used implicit default value for signal "x_5A_RXP8" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 125
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(126): used implicit default value for signal "x_5A_RXN8" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 126
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(129): used implicit default value for signal "x_5A_TXP7" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 129
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(130): used implicit default value for signal "x_5A_TXN7" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 130
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(135): used implicit default value for signal "x_7A_RXN1" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 135
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(137): used implicit default value for signal "x_7A_RXN5" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 137
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(138): used implicit default value for signal "x_7A_TXP8" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 138
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(141): used implicit default value for signal "x_7A_RXN9" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 141
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(148): used implicit default value for signal "x_7A_TXN10" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 148
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(158): used implicit default value for signal "x_7A_RXN3" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 158
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(160): used implicit default value for signal "x_7A_RXN7" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 160
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(161): used implicit default value for signal "x_7A_TXP6" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 161
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(174): used implicit default value for signal "x_8A_TXN50" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 174
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(176): used implicit default value for signal "x_8A_TXN52" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 176
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(177): used implicit default value for signal "x_8A_TXP54" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 177
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(183): used implicit default value for signal "x_8A_RXN53" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 183
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(186): used implicit default value for signal "x_8A_TXN56" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 186
Warning (10541): VHDL Signal Declaration warning at FEE_Control.vhd(306): used implicit default value for signal "s_status" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 306
Warning (10036): Verilog HDL or VHDL warning at FEE_Control.vhd(309): object "s_user_set_req" assigned a value but never read File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 309
Warning (10036): Verilog HDL or VHDL warning at FEE_Control.vhd(341): object "s_DATA_FIFO_wrusedw" assigned a value but never read File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 341
Warning (10036): Verilog HDL or VHDL warning at FEE_Control.vhd(403): object "s_acq_ack" assigned a value but never read File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 403
Warning (10036): Verilog HDL or VHDL warning at FEE_Control.vhd(418): object "s_controller_dbg" assigned a value but never read File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 418
Info (12128): Elaborating entity "PLL_60" for hierarchy "PLL_60:C_PLL" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 456
Info (12128): Elaborating entity "PLL_60_0002" for hierarchy "PLL_60:C_PLL|PLL_60_0002:pll_60_inst" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/PLL_GPIO/PLL_60.vhd Line: 38
Info (12128): Elaborating entity "altera_pll" for hierarchy "PLL_60:C_PLL|PLL_60_0002:pll_60_inst|altera_pll:altera_pll_i" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/PLL_GPIO/PLL_60/PLL_60_0002.v Line: 94
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus
Info (12130): Elaborated megafunction instantiation "PLL_60:C_PLL|PLL_60_0002:pll_60_inst|altera_pll:altera_pll_i" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/PLL_GPIO/PLL_60/PLL_60_0002.v Line: 94
Info (12133): Instantiated megafunction "PLL_60:C_PLL|PLL_60_0002:pll_60_inst|altera_pll:altera_pll_i" with the following parameter: File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/PLL_GPIO/PLL_60/PLL_60_0002.v Line: 94
    Info (12134): Parameter "fractional_vco_multiplier" = "false"
    Info (12134): Parameter "reference_clock_frequency" = "40.0 MHz"
    Info (12134): Parameter "operation_mode" = "direct"
    Info (12134): Parameter "number_of_clocks" = "4"
    Info (12134): Parameter "output_clock_frequency0" = "60.000000 MHz"
    Info (12134): Parameter "phase_shift0" = "0 ps"
    Info (12134): Parameter "duty_cycle0" = "50"
    Info (12134): Parameter "output_clock_frequency1" = "32.000000 MHz"
    Info (12134): Parameter "phase_shift1" = "0 ps"
    Info (12134): Parameter "duty_cycle1" = "50"
    Info (12134): Parameter "output_clock_frequency2" = "15.000000 MHz"
    Info (12134): Parameter "phase_shift2" = "0 ps"
    Info (12134): Parameter "duty_cycle2" = "50"
    Info (12134): Parameter "output_clock_frequency3" = "40.000000 MHz"
    Info (12134): Parameter "phase_shift3" = "0 ps"
    Info (12134): Parameter "duty_cycle3" = "50"
    Info (12134): Parameter "output_clock_frequency4" = "0 MHz"
    Info (12134): Parameter "phase_shift4" = "0 ps"
    Info (12134): Parameter "duty_cycle4" = "50"
    Info (12134): Parameter "output_clock_frequency5" = "0 MHz"
    Info (12134): Parameter "phase_shift5" = "0 ps"
    Info (12134): Parameter "duty_cycle5" = "50"
    Info (12134): Parameter "output_clock_frequency6" = "0 MHz"
    Info (12134): Parameter "phase_shift6" = "0 ps"
    Info (12134): Parameter "duty_cycle6" = "50"
    Info (12134): Parameter "output_clock_frequency7" = "0 MHz"
    Info (12134): Parameter "phase_shift7" = "0 ps"
    Info (12134): Parameter "duty_cycle7" = "50"
    Info (12134): Parameter "output_clock_frequency8" = "0 MHz"
    Info (12134): Parameter "phase_shift8" = "0 ps"
    Info (12134): Parameter "duty_cycle8" = "50"
    Info (12134): Parameter "output_clock_frequency9" = "0 MHz"
    Info (12134): Parameter "phase_shift9" = "0 ps"
    Info (12134): Parameter "duty_cycle9" = "50"
    Info (12134): Parameter "output_clock_frequency10" = "0 MHz"
    Info (12134): Parameter "phase_shift10" = "0 ps"
    Info (12134): Parameter "duty_cycle10" = "50"
    Info (12134): Parameter "output_clock_frequency11" = "0 MHz"
    Info (12134): Parameter "phase_shift11" = "0 ps"
    Info (12134): Parameter "duty_cycle11" = "50"
    Info (12134): Parameter "output_clock_frequency12" = "0 MHz"
    Info (12134): Parameter "phase_shift12" = "0 ps"
    Info (12134): Parameter "duty_cycle12" = "50"
    Info (12134): Parameter "output_clock_frequency13" = "0 MHz"
    Info (12134): Parameter "phase_shift13" = "0 ps"
    Info (12134): Parameter "duty_cycle13" = "50"
    Info (12134): Parameter "output_clock_frequency14" = "0 MHz"
    Info (12134): Parameter "phase_shift14" = "0 ps"
    Info (12134): Parameter "duty_cycle14" = "50"
    Info (12134): Parameter "output_clock_frequency15" = "0 MHz"
    Info (12134): Parameter "phase_shift15" = "0 ps"
    Info (12134): Parameter "duty_cycle15" = "50"
    Info (12134): Parameter "output_clock_frequency16" = "0 MHz"
    Info (12134): Parameter "phase_shift16" = "0 ps"
    Info (12134): Parameter "duty_cycle16" = "50"
    Info (12134): Parameter "output_clock_frequency17" = "0 MHz"
    Info (12134): Parameter "phase_shift17" = "0 ps"
    Info (12134): Parameter "duty_cycle17" = "50"
    Info (12134): Parameter "pll_type" = "General"
    Info (12134): Parameter "pll_subtype" = "General"
Info (12128): Elaborating entity "UFP_WRAPPER_USB_UART" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 470
Info (12128): Elaborating entity "USB_USB_Reader" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB" File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 205
Info (12128): Elaborating entity "USB_UC_PCLK" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK" File: J:/vhdl_db/trunk/lib/usb_usb/src/USB_USB_Reader.vhd Line: 87
Info (12128): Elaborating entity "altddio_out" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component" File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 60
Info (12130): Elaborated megafunction instantiation "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component" File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 60
Info (12133): Instantiated megafunction "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component" with the following parameter: File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_UC_PCLK.vhd Line: 60
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "extend_oe_disable" = "OFF"
    Info (12134): Parameter "invert_output" = "OFF"
    Info (12134): Parameter "oe_reg" = "UNREGISTERED"
    Info (12134): Parameter "power_up_high" = "OFF"
    Info (12134): Parameter "width" = "1"
    Info (12134): Parameter "lpm_hint" = "UNUSED"
    Info (12134): Parameter "lpm_type" = "altddio_out"
Info (12021): Found 1 design units, including 1 entities, in source file db/ddio_out_b2j.tdf
    Info (12023): Found entity 1: ddio_out_b2j File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/ddio_out_b2j.tdf Line: 27
Info (12128): Elaborating entity "ddio_out_b2j" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_USB_Reader:C_USB|USB_UC_PCLK:C_UC_PCLK|altddio_out:ALTDDIO_OUT_component|ddio_out_b2j:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altddio_out.tdf Line: 100
Info (12128): Elaborating entity "USB_L2_TX_FIFO" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX" File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 242
Info (12128): Elaborating entity "dcfifo" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd Line: 104
Info (12130): Elaborated megafunction instantiation "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd Line: 104
Info (12133): Instantiated megafunction "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component" with the following parameter: File: J:/vhdl_db/trunk/lib/usb_usb/c_cyclone5/src/USB_L2_TX_FIFO.vhd Line: 104
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "64"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "33"
    Info (12134): Parameter "lpm_widthu" = "6"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_85n1.tdf
    Info (12023): Found entity 1: dcfifo_85n1 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_85n1.tdf Line: 40
Info (12128): Elaborating entity "dcfifo_85n1" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf Line: 190
Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_e9b.tdf
    Info (12023): Found entity 1: a_gray2bin_e9b File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_gray2bin_e9b.tdf Line: 22
Info (12128): Elaborating entity "a_gray2bin_e9b" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_gray2bin_e9b:rdptr_g_gray2bin" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_85n1.tdf Line: 54
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_bg6.tdf
    Info (12023): Found entity 1: a_graycounter_bg6 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_bg6.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_bg6" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_bg6:rdptr_g1p" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_85n1.tdf Line: 58
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_7ub.tdf
    Info (12023): Found entity 1: a_graycounter_7ub File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_7ub.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_7ub" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|a_graycounter_7ub:wrptr_g1p" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_85n1.tdf Line: 59
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_cia1.tdf
    Info (12023): Found entity 1: altsyncram_cia1 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_cia1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_cia1" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|altsyncram_cia1:fifo_ram" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_85n1.tdf Line: 60
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_vu8.tdf
    Info (12023): Found entity 1: dffpipe_vu8 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_vu8.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_vu8" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|dffpipe_vu8:rs_brp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_85n1.tdf Line: 67
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_f9l.tdf
    Info (12023): Found entity 1: alt_synch_pipe_f9l File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_f9l.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_f9l" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_85n1.tdf Line: 69
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_0v8.tdf
    Info (12023): Found entity 1: dffpipe_0v8 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_0v8.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_0v8" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_f9l:rs_dgwp|dffpipe_0v8:dffpipe13" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_f9l.tdf Line: 33
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_g9l.tdf
    Info (12023): Found entity 1: alt_synch_pipe_g9l File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_g9l.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_g9l" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_85n1.tdf Line: 72
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_1v8.tdf
    Info (12023): Found entity 1: dffpipe_1v8 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_1v8.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_1v8" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|alt_synch_pipe_g9l:ws_dgrp|dffpipe_1v8:dffpipe16" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_g9l.tdf Line: 33
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_vu5.tdf
    Info (12023): Found entity 1: cmpr_vu5 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cmpr_vu5.tdf Line: 22
Info (12128): Elaborating entity "cmpr_vu5" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|USB_L2_TX_FIFO:C_FIFO_READOUT_TX|dcfifo:dcfifo_component|dcfifo_85n1:auto_generated|cmpr_vu5:rdempty_eq_comp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_85n1.tdf Line: 79
Info (12128): Elaborating entity "ser_crc_pol16_DIN16_D4_1a2eb" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC" File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 257
Info (12128): Elaborating entity "ser_crc" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_crc_pol16_DIN16_D4_1a2eb:C_CRC|ser_crc:C_CRC" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/crc_pol/ser_crc_pol16_DIN16_D4_1a2eb.vhd Line: 47
Info (12128): Elaborating entity "UFP_ENCODER_UART" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_ENCODER_UART:C_ENCODER" File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 271
Info (12128): Elaborating entity "UFP_DECODER" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|UFP_DECODER:C_DECODER" File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 326
Info (12128): Elaborating entity "ser_uart_wrapper" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART" File: J:/vhdl_db/trunk/lib/UFP_UsbFrontEndProtocol/src/UFP_WRAPPER_USB_uart.vhd Line: 389
Warning (10541): VHDL Signal Declaration warning at ser_uart_wrapper.vhd(77): used implicit default value for signal "sl_int_fifoRX_rd_usedw" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper.vhd Line: 77
Info (12128): Elaborating entity "ser_uart_wrapper32" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper.vhd Line: 315
Info (12128): Elaborating entity "ser_uart" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper32.vhd Line: 92
Info (12128): Elaborating entity "ser_uart_bdgen" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_bdgen:\g_dbgen:C_BDGEN" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart.vhd Line: 88
Info (12128): Elaborating entity "ser_uart_ser" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_ser:C_SER" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart.vhd Line: 119
Info (12128): Elaborating entity "ser_uart_deser" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart.vhd Line: 143
Info (12128): Elaborating entity "ser_data_5_bits_filter" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|ser_uart:C_UART|ser_uart_deser:C_DESER|ser_data_5_bits_filter:C_FILTER_SIN" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_deser.vhd Line: 83
Info (12128): Elaborating entity "SER_UART_FIFO_TX32" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper32.vhd Line: 123
Info (12128): Elaborating entity "dcfifo_mixed_widths" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd Line: 106
Info (12130): Elaborated megafunction instantiation "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd Line: 106
Info (12133): Instantiated megafunction "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component" with the following parameter: File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_TX32.vhd Line: 106
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "64"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo_mixed_widths"
    Info (12134): Parameter "lpm_width" = "32"
    Info (12134): Parameter "lpm_widthu" = "6"
    Info (12134): Parameter "lpm_widthu_r" = "8"
    Info (12134): Parameter "lpm_width_r" = "8"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_8tq1.tdf
    Info (12023): Found entity 1: dcfifo_8tq1 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_8tq1.tdf Line: 42
Info (12128): Elaborating entity "dcfifo_8tq1" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo_mixed_widths.tdf Line: 78
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_cu6.tdf
    Info (12023): Found entity 1: a_graycounter_cu6 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_cu6.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_cu6" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_cu6:rdptr_g1p" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_8tq1.tdf Line: 58
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_9cc.tdf
    Info (12023): Found entity 1: a_graycounter_9cc File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_9cc.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_9cc" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|a_graycounter_9cc:wrptr_g1p" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_8tq1.tdf Line: 59
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_po91.tdf
    Info (12023): Found entity 1: altsyncram_po91 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_po91.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_po91" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|altsyncram_po91:fifo_ram" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_8tq1.tdf Line: 60
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_unl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_unl File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_unl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_unl" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_8tq1.tdf Line: 65
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_fd9.tdf
    Info (12023): Found entity 1: dffpipe_fd9 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_fd9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_fd9" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_unl:rs_dgwp|dffpipe_fd9:dffpipe12" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_unl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_ed9.tdf
    Info (12023): Found entity 1: dffpipe_ed9 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_ed9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_ed9" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|dffpipe_ed9:ws_brp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_8tq1.tdf Line: 66
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_vnl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_vnl File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_vnl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_vnl" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_8tq1.tdf Line: 68
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_gd9.tdf
    Info (12023): Found entity 1: dffpipe_gd9 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_gd9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_gd9" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|alt_synch_pipe_vnl:ws_dgrp|dffpipe_gd9:dffpipe16" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_vnl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_osd.tdf
    Info (12023): Found entity 1: cntr_osd File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cntr_osd.tdf Line: 27
Info (12128): Elaborating entity "cntr_osd" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_TX32:C_FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_8tq1:auto_generated|cntr_osd:cntr_b" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_8tq1.tdf Line: 74
Info (12128): Elaborating entity "SER_UART_FIFO_RX32" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_uart_wrapper32.vhd Line: 138
Info (12128): Elaborating entity "dcfifo_mixed_widths" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd Line: 102
Info (12130): Elaborated megafunction instantiation "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component" File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd Line: 102
Info (12133): Instantiated megafunction "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component" with the following parameter: File: J:/vhdl_db/trunk/lib/ser_serialCommunication/c_cyclone5/src/SER_UART_FIFO_RX32.vhd Line: 102
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "256"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo_mixed_widths"
    Info (12134): Parameter "lpm_width" = "8"
    Info (12134): Parameter "lpm_widthu" = "8"
    Info (12134): Parameter "lpm_widthu_r" = "6"
    Info (12134): Parameter "lpm_width_r" = "32"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_a5q1.tdf
    Info (12023): Found entity 1: dcfifo_a5q1 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_a5q1.tdf Line: 38
Info (12128): Elaborating entity "dcfifo_a5q1" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo_mixed_widths.tdf Line: 78
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_du6.tdf
    Info (12023): Found entity 1: a_graycounter_du6 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_du6.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_du6" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_du6:rdptr_g1p" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_a5q1.tdf Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_8cc.tdf
    Info (12023): Found entity 1: a_graycounter_8cc File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_8cc.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_8cc" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|a_graycounter_8cc:wrptr_g1p" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_a5q1.tdf Line: 52
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_qo91.tdf
    Info (12023): Found entity 1: altsyncram_qo91 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_qo91.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_qo91" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|altsyncram_qo91:fifo_ram" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_a5q1.tdf Line: 53
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_0ol.tdf
    Info (12023): Found entity 1: alt_synch_pipe_0ol File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_0ol.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_0ol" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_a5q1.tdf Line: 57
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_hd9.tdf
    Info (12023): Found entity 1: dffpipe_hd9 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_hd9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_hd9" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_0ol:rs_dgwp|dffpipe_hd9:dffpipe12" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_0ol.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_1ol.tdf
    Info (12023): Found entity 1: alt_synch_pipe_1ol File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_1ol.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_1ol" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_a5q1.tdf Line: 58
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_id9.tdf
    Info (12023): Found entity 1: dffpipe_id9 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_id9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_id9" for hierarchy "UFP_WRAPPER_USB_UART:C_WRAPPER_USB|ser_uart_wrapper:C_UART|ser_uart_wrapper32:\g32:u1|SER_UART_FIFO_RX32:C_FIFO_RX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_a5q1:auto_generated|alt_synch_pipe_1ol:ws_dgrp|dffpipe_id9:dffpipe15" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_1ol.tdf Line: 34
Info (12128): Elaborating entity "UGB_DATA_FIFO" for hierarchy "UGB_DATA_FIFO:C_FIFO" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 570
Info (12128): Elaborating entity "dcfifo" for hierarchy "UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/UGB_DATA_FIFO.vhd Line: 108
Info (12130): Elaborated megafunction instantiation "UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/UGB_DATA_FIFO.vhd Line: 108
Info (12133): Instantiated megafunction "UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component" with the following parameter: File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/UGB_DATA_FIFO.vhd Line: 108
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "1024"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "33"
    Info (12134): Parameter "lpm_widthu" = "10"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_6tr1.tdf
    Info (12023): Found entity 1: dcfifo_6tr1 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_6tr1.tdf Line: 40
Info (12128): Elaborating entity "dcfifo_6tr1" for hierarchy "UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf Line: 190
Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_pab.tdf
    Info (12023): Found entity 1: a_gray2bin_pab File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_gray2bin_pab.tdf Line: 22
Info (12128): Elaborating entity "a_gray2bin_pab" for hierarchy "UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|a_gray2bin_pab:rdptr_g_gray2bin" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_6tr1.tdf Line: 55
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_ov6.tdf
    Info (12023): Found entity 1: a_graycounter_ov6 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_ov6.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_ov6" for hierarchy "UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|a_graycounter_ov6:rdptr_g1p" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_6tr1.tdf Line: 59
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_kdc.tdf
    Info (12023): Found entity 1: a_graycounter_kdc File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_kdc.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_kdc" for hierarchy "UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|a_graycounter_kdc:wrptr_g1p" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_6tr1.tdf Line: 60
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_m8d1.tdf
    Info (12023): Found entity 1: altsyncram_m8d1 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_m8d1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_m8d1" for hierarchy "UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|altsyncram_m8d1:fifo_ram" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_6tr1.tdf Line: 61
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf
    Info (12023): Found entity 1: dffpipe_pe9 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_pe9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_pe9" for hierarchy "UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|dffpipe_pe9:rs_brp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_6tr1.tdf Line: 68
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_9pl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_9pl File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_9pl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_9pl" for hierarchy "UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_6tr1.tdf Line: 70
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf
    Info (12023): Found entity 1: dffpipe_qe9 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_qe9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_qe9" for hierarchy "UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_9pl:rs_dgwp|dffpipe_qe9:dffpipe13" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_9pl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_apl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_apl File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_apl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_apl" for hierarchy "UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_6tr1.tdf Line: 73
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_re9.tdf
    Info (12023): Found entity 1: dffpipe_re9 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_re9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_re9" for hierarchy "UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|alt_synch_pipe_apl:ws_dgrp|dffpipe_re9:dffpipe16" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_apl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_a06.tdf
    Info (12023): Found entity 1: cmpr_a06 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cmpr_a06.tdf Line: 22
Info (12128): Elaborating entity "cmpr_a06" for hierarchy "UGB_DATA_FIFO:C_FIFO|dcfifo:dcfifo_component|dcfifo_6tr1:auto_generated|cmpr_a06:rdempty_eq_comp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_6tr1.tdf Line: 80
Info (12128): Elaborating entity "UGB_CFG_DPRAM" for hierarchy "UGB_CFG_DPRAM:C_DPRAM" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 590
Info (12128): Elaborating entity "altsyncram" for hierarchy "UGB_CFG_DPRAM:C_DPRAM|altsyncram:altsyncram_component" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/UGB_CFG_DPRAM.vhd Line: 62
Info (12130): Elaborated megafunction instantiation "UGB_CFG_DPRAM:C_DPRAM|altsyncram:altsyncram_component" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/UGB_CFG_DPRAM.vhd Line: 62
Info (12133): Instantiated megafunction "UGB_CFG_DPRAM:C_DPRAM|altsyncram:altsyncram_component" with the following parameter: File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/UGB_CFG_DPRAM.vhd Line: 62
    Info (12134): Parameter "address_aclr_a" = "UNUSED"
    Info (12134): Parameter "address_aclr_b" = "NONE"
    Info (12134): Parameter "address_reg_b" = "CLOCK0"
    Info (12134): Parameter "byte_size" = "8"
    Info (12134): Parameter "byteena_aclr_a" = "UNUSED"
    Info (12134): Parameter "byteena_aclr_b" = "NONE"
    Info (12134): Parameter "byteena_reg_b" = "CLOCK1"
    Info (12134): Parameter "clock_enable_core_a" = "USE_INPUT_CLKEN"
    Info (12134): Parameter "clock_enable_core_b" = "USE_INPUT_CLKEN"
    Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
    Info (12134): Parameter "clock_enable_input_b" = "BYPASS"
    Info (12134): Parameter "clock_enable_output_a" = "NORMAL"
    Info (12134): Parameter "clock_enable_output_b" = "BYPASS"
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "ecc_pipeline_stage_enabled" = "FALSE"
    Info (12134): Parameter "enable_ecc" = "FALSE"
    Info (12134): Parameter "implement_in_les" = "OFF"
    Info (12134): Parameter "indata_aclr_a" = "UNUSED"
    Info (12134): Parameter "indata_aclr_b" = "NONE"
    Info (12134): Parameter "indata_reg_b" = "CLOCK1"
    Info (12134): Parameter "init_file" = "UNUSED"
    Info (12134): Parameter "init_file_layout" = "PORT_A"
    Info (12134): Parameter "maximum_depth" = "0"
    Info (12134): Parameter "numwords_a" = "1024"
    Info (12134): Parameter "numwords_b" = "1024"
    Info (12134): Parameter "operation_mode" = "DUAL_PORT"
    Info (12134): Parameter "outdata_aclr_a" = "NONE"
    Info (12134): Parameter "outdata_aclr_b" = "NONE"
    Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
    Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"
    Info (12134): Parameter "power_up_uninitialized" = "FALSE"
    Info (12134): Parameter "ram_block_type" = "AUTO"
    Info (12134): Parameter "rdcontrol_aclr_b" = "NONE"
    Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK1"
    Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
    Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ"
    Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ"
    Info (12134): Parameter "stratixiv_m144k_allow_dual_clocks" = "ON"
    Info (12134): Parameter "width_a" = "16"
    Info (12134): Parameter "width_b" = "16"
    Info (12134): Parameter "width_byteena_a" = "1"
    Info (12134): Parameter "width_byteena_b" = "1"
    Info (12134): Parameter "width_eccstatus" = "3"
    Info (12134): Parameter "widthad_a" = "10"
    Info (12134): Parameter "widthad_b" = "10"
    Info (12134): Parameter "wrcontrol_aclr_a" = "UNUSED"
    Info (12134): Parameter "wrcontrol_aclr_b" = "NONE"
    Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1"
    Info (12134): Parameter "lpm_hint" = "UNUSED"
    Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_s1v3.tdf
    Info (12023): Found entity 1: altsyncram_s1v3 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_s1v3.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_s1v3" for hierarchy "UGB_CFG_DPRAM:C_DPRAM|altsyncram:altsyncram_component|altsyncram_s1v3:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 791
Info (12128): Elaborating entity "USER_GET_CONFIG_RANGE_RD" for hierarchy "USER_GET_CONFIG_RANGE_RD:C_HOUSEKEEPING_USER_GET" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 607
Info (12128): Elaborating entity "USER_GET_CONFIG_RANGE_RD" for hierarchy "USER_GET_CONFIG_RANGE_RD:C_PEDESTALS_USER_GET" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 637
Info (12128): Elaborating entity "UFP_USER_SETGET_ACK" for hierarchy "UFP_USER_SETGET_ACK:C_GET_ACK" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 681
Info (12129): Elaborating entity "serdes" using architecture "A:a_serdes" for hierarchy "serdes:SERDES" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 694
Info (12128): Elaborating entity "GCLK" for hierarchy "serdes:SERDES|GCLK:RxClk_Buf" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/Serdes.vhd Line: 134
Info (12128): Elaborating entity "GCLK_altclkctrl_0" for hierarchy "serdes:SERDES|GCLK:RxClk_Buf|GCLK_altclkctrl_0:altclkctrl_0" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/ip/gclk/gclk.v Line: 14
Info (12128): Elaborating entity "GCLK_altclkctrl_0_sub" for hierarchy "serdes:SERDES|GCLK:RxClk_Buf|GCLK_altclkctrl_0:altclkctrl_0|GCLK_altclkctrl_0_sub:GCLK_altclkctrl_0_sub_component" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/ip/gclk/submodules/gclk_altclkctrl_0.v Line: 102
Warning (10036): Verilog HDL or VHDL warning at gclk_altclkctrl_0.v(46): object "clkselect" assigned a value but never read File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/ip/gclk/submodules/gclk_altclkctrl_0.v Line: 46
Info (12128): Elaborating entity "deserializer" for hierarchy "serdes:SERDES|deserializer:SERIAL_RX" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/Serdes.vhd Line: 200
Info (12129): Elaborating entity "decoder_4b5b" using architecture "A:syn" for hierarchy "serdes:SERDES|deserializer:SERIAL_RX|decoder_4b5b:LSBDECODE" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/Deserializer.vhd Line: 63
Info (12128): Elaborating entity "serializer" for hierarchy "serdes:SERDES|serializer:SERIAL_TX" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/Serdes.vhd Line: 213
Info (12129): Elaborating entity "encoder_4b5b" using architecture "A:syn" for hierarchy "serdes:SERDES|serializer:SERIAL_TX|encoder_4b5b:LSBCODER" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/serial_communication/Serializer.vhd Line: 60
Info (12129): Elaborating entity "SERDES_TX_FIFO" using architecture "A:syn" for hierarchy "SERDES_TX_FIFO:TX_FIFO" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 714
Info (12128): Elaborating entity "dcfifo" for hierarchy "SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/SERDES_TX_FIFO.vhd Line: 100
Info (12130): Elaborated megafunction instantiation "SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/SERDES_TX_FIFO.vhd Line: 100
Info (12133): Instantiated megafunction "SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component" with the following parameter: File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/SERDES_TX_FIFO.vhd Line: 100
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "1024"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "9"
    Info (12134): Parameter "lpm_widthu" = "10"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_t7q1.tdf
    Info (12023): Found entity 1: dcfifo_t7q1 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_t7q1.tdf Line: 36
Info (12128): Elaborating entity "dcfifo_t7q1" for hierarchy "SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf Line: 190
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_s5d1.tdf
    Info (12023): Found entity 1: altsyncram_s5d1 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_s5d1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_s5d1" for hierarchy "SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|altsyncram_s5d1:fifo_ram" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_t7q1.tdf Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_bpl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_bpl File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_bpl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_bpl" for hierarchy "SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_t7q1.tdf Line: 58
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_se9.tdf
    Info (12023): Found entity 1: dffpipe_se9 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_se9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_se9" for hierarchy "SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_bpl:rs_dgwp|dffpipe_se9:dffpipe6" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_bpl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_cpl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_cpl File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_cpl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_cpl" for hierarchy "SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_t7q1.tdf Line: 59
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_te9.tdf
    Info (12023): Found entity 1: dffpipe_te9 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_te9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_te9" for hierarchy "SERDES_TX_FIFO:TX_FIFO|dcfifo:dcfifo_component|dcfifo_t7q1:auto_generated|alt_synch_pipe_cpl:ws_dgrp|dffpipe_te9:dffpipe9" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_cpl.tdf Line: 34
Info (12129): Elaborating entity "SERDES_RX_FIFO" using architecture "A:syn" for hierarchy "SERDES_RX_FIFO:RX_FIFO" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 728
Info (12128): Elaborating entity "dcfifo" for hierarchy "SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/SERDES_RX_FIFO.vhd Line: 100
Info (12130): Elaborated megafunction instantiation "SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/SERDES_RX_FIFO.vhd Line: 100
Info (12133): Instantiated megafunction "SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component" with the following parameter: File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/SERDES_RX_FIFO.vhd Line: 100
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "16"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_width" = "8"
    Info (12134): Parameter "lpm_widthu" = "4"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "rdsync_delaypipe" = "4"
    Info (12134): Parameter "read_aclr_synch" = "OFF"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "write_aclr_synch" = "OFF"
    Info (12134): Parameter "wrsync_delaypipe" = "4"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_12q1.tdf
    Info (12023): Found entity 1: dcfifo_12q1 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_12q1.tdf Line: 36
Info (12128): Elaborating entity "dcfifo_12q1" for hierarchy "SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/dcfifo.tdf Line: 190
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_bu6.tdf
    Info (12023): Found entity 1: a_graycounter_bu6 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_bu6.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_bu6" for hierarchy "SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|a_graycounter_bu6:rdptr_g1p" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_12q1.tdf Line: 49
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_7cc.tdf
    Info (12023): Found entity 1: a_graycounter_7cc File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_graycounter_7cc.tdf Line: 24
Info (12128): Elaborating entity "a_graycounter_7cc" for hierarchy "SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|a_graycounter_7cc:wrptr_g1p" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_12q1.tdf Line: 50
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_03d1.tdf
    Info (12023): Found entity 1: altsyncram_03d1 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_03d1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_03d1" for hierarchy "SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|altsyncram_03d1:fifo_ram" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_12q1.tdf Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_snl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_snl File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_snl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_snl" for hierarchy "SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_12q1.tdf Line: 58
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_dd9.tdf
    Info (12023): Found entity 1: dffpipe_dd9 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_dd9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_dd9" for hierarchy "SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_snl:rs_dgwp|dffpipe_dd9:dffpipe10" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_snl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_tnl.tdf
    Info (12023): Found entity 1: alt_synch_pipe_tnl File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_tnl.tdf Line: 26
Info (12128): Elaborating entity "alt_synch_pipe_tnl" for hierarchy "SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_12q1.tdf Line: 59
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_jd9.tdf
    Info (12023): Found entity 1: dffpipe_jd9 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dffpipe_jd9.tdf Line: 24
Info (12128): Elaborating entity "dffpipe_jd9" for hierarchy "SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|alt_synch_pipe_tnl:ws_dgrp|dffpipe_jd9:dffpipe13" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/alt_synch_pipe_tnl.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_tu5.tdf
    Info (12023): Found entity 1: cmpr_tu5 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cmpr_tu5.tdf Line: 22
Info (12128): Elaborating entity "cmpr_tu5" for hierarchy "SERDES_RX_FIFO:RX_FIFO|dcfifo:dcfifo_component|dcfifo_12q1:auto_generated|cmpr_tu5:rdempty_eq_comp" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/dcfifo_12q1.tdf Line: 60
Info (12129): Elaborating entity "fee_controller" using architecture "A:syn" for hierarchy "fee_controller:C_FEECONTROLLER" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 771
Info (12129): Elaborating entity "L0_FIFO" using architecture "A:syn" for hierarchy "L0_FIFO:C_L0_FIFO" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 808
Info (12128): Elaborating entity "scfifo" for hierarchy "L0_FIFO:C_L0_FIFO|scfifo:scfifo_component" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/L0_FIFO.vhd Line: 95
Info (12130): Elaborated megafunction instantiation "L0_FIFO:C_L0_FIFO|scfifo:scfifo_component" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/L0_FIFO.vhd Line: 95
Info (12133): Instantiated megafunction "L0_FIFO:C_L0_FIFO|scfifo:scfifo_component" with the following parameter: File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/L0_FIFO.vhd Line: 95
    Info (12134): Parameter "add_ram_output_register" = "OFF"
    Info (12134): Parameter "intended_device_family" = "Cyclone V"
    Info (12134): Parameter "lpm_numwords" = "64"
    Info (12134): Parameter "lpm_showahead" = "ON"
    Info (12134): Parameter "lpm_type" = "scfifo"
    Info (12134): Parameter "lpm_width" = "32"
    Info (12134): Parameter "lpm_widthu" = "6"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_3e91.tdf
    Info (12023): Found entity 1: scfifo_3e91 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/scfifo_3e91.tdf Line: 24
Info (12128): Elaborating entity "scfifo_3e91" for hierarchy "L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated" File: c:/intelfpga/18.0/quartus/libraries/megafunctions/scfifo.tdf Line: 299
Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_ak91.tdf
    Info (12023): Found entity 1: a_dpfifo_ak91 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_dpfifo_ak91.tdf Line: 32
Info (12128): Elaborating entity "a_dpfifo_ak91" for hierarchy "L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/scfifo_3e91.tdf Line: 36
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_j0i1.tdf
    Info (12023): Found entity 1: altsyncram_j0i1 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/altsyncram_j0i1.tdf Line: 27
Info (12128): Elaborating entity "altsyncram_j0i1" for hierarchy "L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo|altsyncram_j0i1:FIFOram" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_dpfifo_ak91.tdf Line: 45
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_5l8.tdf
    Info (12023): Found entity 1: cmpr_5l8 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cmpr_5l8.tdf Line: 22
Info (12128): Elaborating entity "cmpr_5l8" for hierarchy "L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo|cmpr_5l8:almost_full_comparer" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_dpfifo_ak91.tdf Line: 54
Info (12128): Elaborating entity "cmpr_5l8" for hierarchy "L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo|cmpr_5l8:three_comparison" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_dpfifo_ak91.tdf Line: 55
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_igb.tdf
    Info (12023): Found entity 1: cntr_igb File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cntr_igb.tdf Line: 25
Info (12128): Elaborating entity "cntr_igb" for hierarchy "L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo|cntr_igb:rd_ptr_msb" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_dpfifo_ak91.tdf Line: 56
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_vg7.tdf
    Info (12023): Found entity 1: cntr_vg7 File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cntr_vg7.tdf Line: 25
Info (12128): Elaborating entity "cntr_vg7" for hierarchy "L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo|cntr_vg7:usedw_counter" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_dpfifo_ak91.tdf Line: 57
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_jgb.tdf
    Info (12023): Found entity 1: cntr_jgb File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/cntr_jgb.tdf Line: 25
Info (12128): Elaborating entity "cntr_jgb" for hierarchy "L0_FIFO:C_L0_FIFO|scfifo:scfifo_component|scfifo_3e91:auto_generated|a_dpfifo_ak91:dpfifo|cntr_jgb:wr_ptr" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/db/a_dpfifo_ak91.tdf Line: 58
Warning (13034): The following nodes have both tri-state and non-tri-state drivers
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[0]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[1]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[2]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[3]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[4]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[5]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[6]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[7]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[8]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[9]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[10]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[11]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[12]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[13]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[14]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[15]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[16]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[17]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[18]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[19]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[20]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[21]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[22]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[23]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[24]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[25]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[26]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[27]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[28]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[29]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[30]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13035): Inserted always-enabled tri-state buffer between "x_UC_DQ[31]" and its non-tri-state driver. File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
Warning (13039): The following bidirectional pins have no drivers
    Warning (13040): bidirectional pin "x_ADC_SDIO" has no driver File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 21
Warning (13032): The following tri-state nodes are fed by constants
    Warning (13033): The pin "x_IO_8A[0]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[1]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[2]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[3]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[4]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[5]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[6]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[7]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[8]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[9]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[10]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[11]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[12]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[13]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[14]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
    Warning (13033): The pin "x_IO_8A[15]" is fed by GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 48
Info (13000): Registers with preset signals will power-up high File: J:/vhdl_db/trunk/lib/ser_serialCommunication/src/ser_crc.vhd Line: 148
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (13009): TRI or OPNDRN buffers permanently enabled
    Warning (13010): Node "x_UC_DQ[0]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[1]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[2]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[3]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[4]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[5]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[6]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[7]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[8]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[9]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[10]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[11]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[12]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[13]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[14]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[15]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[16]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[17]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[18]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[19]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[20]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[21]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[22]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[23]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[24]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[25]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[26]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[27]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[28]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[29]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[30]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
    Warning (13010): Node "x_UC_DQ[31]~synth" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 24
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "x_ADC_CLK" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 18
    Warning (13410): Pin "x_ADC_SCLK" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 19
    Warning (13410): Pin "x_ADC_CSB" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 20
    Warning (13410): Pin "x_UC_SLRDn" is stuck at VCC File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 28
    Warning (13410): Pin "x_UC_SLOEn" is stuck at VCC File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 29
    Warning (13410): Pin "x_UC_A[0]" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 31
    Warning (13410): Pin "x_UC_A[1]" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 31
    Warning (13410): Pin "x_UC_UART_CTSn" is stuck at VCC File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 39
    Warning (13410): Pin "x_DAC_CS" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 43
    Warning (13410): Pin "x_DAC_SDI" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 44
    Warning (13410): Pin "x_DAC_SCK" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 45
    Warning (13410): Pin "x_3B_TX33" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 57
    Warning (13410): Pin "x_3B_TX25" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 62
    Warning (13410): Pin "x_3B_TX29" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 64
    Warning (13410): Pin "x_3B_TX32" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 65
    Warning (13410): Pin "x_3B_TX40" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 66
    Warning (13410): Pin "x_4A_TX57" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 70
    Warning (13410): Pin "x_4A_TX60" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 71
    Warning (13410): Pin "x_4A_TX64" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 73
    Warning (13410): Pin "x_4A_TXP49" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 76
    Warning (13410): Pin "x_4A_TXN49" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 77
    Warning (13410): Pin "x_4A_TXP53" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 78
    Warning (13410): Pin "x_4A_TXP41" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 81
    Warning (13410): Pin "x_4A_TXN41" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 82
    Warning (13410): Pin "x_4A_TXP45" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 83
    Warning (13410): Pin "x_4A_TXN56" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 87
    Warning (13410): Pin "x_4A_RXP59" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 89
    Warning (13410): Pin "x_4A_RXN59" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 90
    Warning (13410): Pin "x_4A_TXP61" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 91
    Warning (13410): Pin "x_4A_TXN61" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 92
    Warning (13410): Pin "x_4A_TXN52" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 95
    Warning (13410): Pin "x_3B_TXP28" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 97
    Warning (13410): Pin "x_3B_TXN28" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 98
    Warning (13410): Pin "x_4A_TXP44" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 99
    Warning (13410): Pin "x_4A_TXN44" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 100
    Warning (13410): Pin "x_5A_TXP1" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 121
    Warning (13410): Pin "x_5A_TXN1" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 122
    Warning (13410): Pin "x_5A_RXP8" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 125
    Warning (13410): Pin "x_5A_RXN8" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 126
    Warning (13410): Pin "x_5A_TXP7" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 129
    Warning (13410): Pin "x_5A_TXN7" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 130
    Warning (13410): Pin "x_7A_RXN1" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 135
    Warning (13410): Pin "x_7A_RXN5" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 137
    Warning (13410): Pin "x_7A_TXP8" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 138
    Warning (13410): Pin "x_7A_RXN9" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 141
    Warning (13410): Pin "x_7A_TXN10" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 148
    Warning (13410): Pin "x_7A_RXN3" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 158
    Warning (13410): Pin "x_7A_RXN7" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 160
    Warning (13410): Pin "x_7A_TXP6" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 161
    Warning (13410): Pin "x_8A_TXN50" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 174
    Warning (13410): Pin "x_8A_TXN52" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 176
    Warning (13410): Pin "x_8A_TXP54" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 177
    Warning (13410): Pin "x_8A_RXN53" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 183
    Warning (13410): Pin "x_8A_TXN56" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 186
    Warning (13410): Pin "x_NIM_OUT" is stuck at GND File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 190
Info (286030): Timing-Driven Synthesis is running
Info (17049): 12 registers lost all their fanouts during netlist optimizations.
Info (17016): Found the following redundant logic cells in design
    Info (17048): Logic cell "s_usb_ready" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 293
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 16 node(s), including 1 DDIO, 4 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 66 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "x_ADC_OUT[0]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 15
    Warning (15610): No output dependent on input pin "x_ADC_OUT[1]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 15
    Warning (15610): No output dependent on input pin "x_ADC_OUT[2]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 15
    Warning (15610): No output dependent on input pin "x_ADC_OUT[3]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 15
    Warning (15610): No output dependent on input pin "x_ADC_OUT[4]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 15
    Warning (15610): No output dependent on input pin "x_ADC_OUT[5]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 15
    Warning (15610): No output dependent on input pin "x_ADC_OUT[6]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 15
    Warning (15610): No output dependent on input pin "x_ADC_OUT[7]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 15
    Warning (15610): No output dependent on input pin "x_ADC_FCO" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 16
    Warning (15610): No output dependent on input pin "x_ADC_DCO" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 17
    Warning (15610): No output dependent on input pin "x_UC_FLAGS[1]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 32
    Warning (15610): No output dependent on input pin "x_UC_FLAGS[2]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 32
    Warning (15610): No output dependent on input pin "x_UC_FLAGS[3]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 32
    Warning (15610): No output dependent on input pin "x_UC_UART_RTSn" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 38
    Warning (15610): No output dependent on input pin "x_3B_RX35" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 51
    Warning (15610): No output dependent on input pin "x_3B_RX38" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 52
    Warning (15610): No output dependent on input pin "x_3B_RX27" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 54
    Warning (15610): No output dependent on input pin "x_3B_RX31" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 55
    Warning (15610): No output dependent on input pin "x_3B_RX30" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 59
    Warning (15610): No output dependent on input pin "x_3B_RX34" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 60
    Warning (15610): No output dependent on input pin "x_3B_RX26" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 63
    Warning (15610): No output dependent on input pin "x_4A_RX62" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 72
    Warning (15610): No output dependent on input pin "x_4A_TXN53" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 79
    Warning (15610): No output dependent on input pin "x_4A_TXN45" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 84
    Warning (15610): No output dependent on input pin "x_4A_TXP56" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 85
    Warning (15610): No output dependent on input pin "x_4A_TXP52" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 93
    Warning (15610): No output dependent on input pin "x_5A_RXP6" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 123
    Warning (15610): No output dependent on input pin "x_5A_RXN6" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 124
    Warning (15610): No output dependent on input pin "x_5A_RXP4" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 127
    Warning (15610): No output dependent on input pin "x_5A_RXN4" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 128
    Warning (15610): No output dependent on input pin "x_5A_RXN2" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 131
    Warning (15610): No output dependent on input pin "x_7A_RXP1" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 134
    Warning (15610): No output dependent on input pin "x_7A_RXP5" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 136
    Warning (15610): No output dependent on input pin "x_7A_TXN8" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 139
    Warning (15610): No output dependent on input pin "x_7A_RXP9" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 140
    Warning (15610): No output dependent on input pin "x_7A_TXP2" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 143
    Warning (15610): No output dependent on input pin "x_7A_RXP3" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 144
    Warning (15610): No output dependent on input pin "x_7A_TXP4" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 145
    Warning (15610): No output dependent on input pin "x_7A_RXP7" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 146
    Warning (15610): No output dependent on input pin "x_7A_TXP10" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 147
    Warning (15610): No output dependent on input pin "x_7A_TXP12" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 149
    Warning (15610): No output dependent on input pin "x_7A_TXN12" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 150
    Warning (15610): No output dependent on input pin "x_7A_TXP14" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 151
    Warning (15610): No output dependent on input pin "x_7A_TXN14" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 152
    Warning (15610): No output dependent on input pin "x_7A_TXP16" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 153
    Warning (15610): No output dependent on input pin "x_7A_TXN16" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 154
    Warning (15610): No output dependent on input pin "x_7A_RXP37" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 155
    Warning (15610): No output dependent on input pin "x_7A_RXN37" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 156
    Warning (15610): No output dependent on input pin "x_7A_TXN2" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 157
    Warning (15610): No output dependent on input pin "x_7A_TXN4" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 159
    Warning (15610): No output dependent on input pin "x_7A_TXN6" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 162
    Warning (15610): No output dependent on input pin "x_8A_TXP50" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 173
    Warning (15610): No output dependent on input pin "x_8A_TXP52" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 175
    Warning (15610): No output dependent on input pin "x_8A_TXN54" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 178
    Warning (15610): No output dependent on input pin "x_8A_TXP56" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 179
    Warning (15610): No output dependent on input pin "x_8A_RXP51" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 180
    Warning (15610): No output dependent on input pin "x_8A_RXN51" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 181
    Warning (15610): No output dependent on input pin "x_8A_RXP55" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 184
    Warning (15610): No output dependent on input pin "x_8A_RXN55" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 185
    Warning (15610): No output dependent on input pin "x_BOARDID[0]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 189
    Warning (15610): No output dependent on input pin "x_BOARDID[1]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 189
    Warning (15610): No output dependent on input pin "x_BOARDID[2]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 189
    Warning (15610): No output dependent on input pin "x_BOARDID[3]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 189
    Warning (15610): No output dependent on input pin "x_NIM_IN[0]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 191
    Warning (15610): No output dependent on input pin "x_NIM_IN[1]" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 191
    Warning (15610): No output dependent on input pin "x_EXT_CLK" File: J:/vhdl_db/trunk/projets/POL_Polar/FEE_Control/src/FEE_Control.vhd Line: 196
Info (21057): Implemented 6922 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 75 input pins
    Info (21059): Implemented 82 output pins
    Info (21060): Implemented 50 bidirectional pins
    Info (21061): Implemented 6562 logic cells
    Info (21064): Implemented 147 RAM segments
    Info (21065): Implemented 4 PLLs
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 258 warnings
    Info: Peak virtual memory: 4980 megabytes
    Info: Processing ended: Wed Jun 18 10:51:35 2025
    Info: Elapsed time: 00:00:19
    Info: Total CPU time (on all processors): 00:00:32


